Display Pipeline Power Gating for Pre-Rendered Image Frames
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Electronic devices face challenges in balancing information communication efficiency with power consumption efficiency, particularly in wearable and portable devices that have limited electrical energy storage, as their electronic displays consume more power when powered-on.
Innovation Solution
Implementing a decoupled electronic display with a display pipeline that pre-renders image frames and stores them in memory, allowing the display to continue displaying images even when the processor is powered-off, and using a second processor to manage power states of the display pipeline.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If the electronic display is kept powered-on to display images continuously, then information communication efficiency is improved, but power consumption increases
Solution Approach 1:
The system pre-renders image frames and stores them in a buffer memory before the processor is powered off. This preliminary action allows the display pipeline to continue operating with stored image data, maintaining information display capability while the processor consumes no power.
Solution Approach 2:
The system separates the display function from the processor by implementing an independent display pipeline that can operate autonomously. The display pipeline is divided into distinct stages (renderer, processor, scaler, formatter) that can function independently once initialized, allowing the main processor to be powered off while display continues.
2Use of energy by moving object
If the processor is powered-off to reduce power consumption, then power efficiency is improved, but the ability to process and display new image data is lost
Solution Approach 1:
The display pipeline is designed to be self-sufficient once initialized. It contains all necessary processing stages and can operate autonomously using stored image data from the buffer, without requiring the main processor. This self-service capability allows the processor to be powered off while display functionality is maintained.
Solution Approach 2:
Image frames are pre-rendered and stored in buffer memory before the processor enters low-power state. This preliminary preparation ensures that the autonomous display pipeline has sufficient image data to continue displaying without interruption, even though the processor will be powered off.
3Use of energy by moving object
If a decoupled display pipeline is implemented to enable processor power-off, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The display pipeline stages (renderer, processor, scaler, formatter) are merged into a single integrated processing chain that shares common resources such as memory interfaces and control logic. This merging reduces overall complexity compared to having completely separate independent display systems, while still enabling autonomous operation.
Solution Approach 2:
The display pipeline is designed with multi-functional components that can handle various image processing tasks. The same pipeline infrastructure serves both processor-driven display mode and autonomous display mode, eliminating the need for completely separate hardware paths and reducing overall system complexity.
Data Source
AI summary
An electronic device may include a display panel to display images based on corresponding image data and an image source to pre-render a flip-book including a first image frame for display at a first target presentation time and a second image frame for display at a second target presentation time. The electronic device may also include a display pipeline coupled between the display panel and the image source having image data processing circuitry to process image data for display. The electronic device may also include a controller to instruct the display pipeline to process image data, to determine a power-on time based on a target presentation time, and to instruct the display pipeline to power-gate the image data processing circuitry upon completion of the processing of image data and until the power-on time is reached.