Display Pixel Bias Circuit for Variable-Frequency Line Defect Control
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Solution Overview
Problem
Display apparatuses experience horizontal line defects due to increased load on gate driving signals during variable frequency operation, leading to reduced display quality.
Innovation Solution
The display apparatus employs a high-frequency bias operation with wider and lower resistance signal lines, dual-layered source-drain metal structures, and adjusted gate driving signals to prevent horizontal line defects by reducing load on bias transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If variable frequency operation is implemented, then adaptability is improved, but horizontal line defects occur due to increased load on gate driving signals
Solution Approach 1:
The patent implements dynamic frequency adjustment capability where the display apparatus can operate at different frequencies (e.g., 60Hz, 120Hz, 240Hz) based on content requirements. The gate driver dynamically changes the frequency of gate signals to match the desired operating mode, enabling adaptability while maintaining display quality through compensated signal design.
Solution Approach 2:
The patent changes multiple parameters simultaneously to resolve the contradiction: (1) increases bias gate signal frequency relative to data write gate signal frequency, (2) adjusts emission signal frequencies to match operating mode, (3) modifies signal line widths and resistances. These parameter changes allow the system to operate at variable frequencies without producing horizontal line defects.
2Reliability
If bias operation frequency is increased, then display quality is improved, but load on bias transistors increases causing horizontal line defects
Solution Approach 1:
The patent changes the frequency parameter of bias gate signals to be higher than that of data write gate signals. This parameter change allows the bias operation to run at optimal frequencies for display quality while the dual-layer source-drain structure handles the increased power load.
Solution Approach 2:
The patent adds a spatial dimension by implementing dual-layer source-drain metal structures. Instead of increasing transistor size in a single plane, the solution moves to three-dimensional stacking with multiple metal layers, thereby reducing the in-plane footprint and load on individual bias transistors while maintaining high bias operation frequency.
3Reliability
If signal line width is increased, then resistance is reduced improving signal quality, but device area increases
Solution Approach 1:
The patent resolves the area-resistance contradiction by transitioning from single-layer to dual-layer source-drain metal structures. The first and second source-drain metals are stacked in different layers, providing parallel current paths that reduce effective resistance without increasing the planar footprint. This vertical stacking approach maintains compact device area while improving signal quality.
Solution Approach 2:
The patent uses composite metal layer structures where multiple metal layers (first source-drain metal and second source-drain metal) work together to provide low-resistance current paths. This composite structure combines the advantages of multiple materials/layers to achieve reduced resistance without the area penalty of a single wide conductor.
Data Source
AI summary
A display apparatus includes a display panel, a gate driver, a data driver and an emission driver. The display panel includes a pixel. The gate driver is configured to provide a gate signal to the pixel. The data driver is configured to provide a data voltage to the pixel. The emission driver is configured to provide an emission signal to the pixel. The pixel includes a light emitting element, a driving switching element and a bias switching element. The driving switching element is configured to apply a driving current to the light emitting element. The bias switching element is configured to provide a bias voltage to an input electrode of the driving switching element. A frequency of a bias gate signal applied to a control electrode of the bias switching element is greater than a frequency of a data write gate signal applied to the pixel.