Display Pixel Layout for Low-Capacitance Light-Sensing Readout

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Solution Overview

Problem

Existing display devices face challenges in enhancing reliability due to coupling capacitance issues between data lines and readout lines, which affect the performance and functionality of integrated light-sensing pixels.

Innovation Solution

The display device incorporates a readout line and a reset voltage wiring in the same layer, with a dummy pattern in the same layer as the data lines, and a bridge pattern electrically connected to the gate electrode of a sensor transistor, which helps maintain a separation distance and reduces coupling capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data lines and readout lines are disposed in different layers, then coupling capacitance between them is reduced, but device complexity increases due to multi-layer wiring structure

Engineering Contradiction:
Improvesignal integrityVSAvoidwiring structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dimensionality change by transitioning from planar arrangement to vertical stacking. Data lines and readout lines are disposed in different layers (vertical dimension) rather than adjacent in the same plane, which reduces coupling capacitance while maintaining a compact footprint. The dummy pattern is also positioned in a different layer to further minimize interference.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If dummy pattern is added to reduce coupling capacitance, then reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvecoupling capacitance controlVSAvoidpattern fabrication
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The dummy pattern serves as an intermediary element positioned between the data line and readout line. This dummy conductor pattern acts as a shield or buffer that reduces the direct coupling capacitance between the functional lines. The dummy pattern is electrically connected to a reference potential to effectively minimize interference while maintaining signal integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If readout line and reset voltage wiring are in the same layer, then device complexity is reduced, but coupling capacitance with data lines increases

Engineering Contradiction:
Improvelayer structureVSAvoidsignal interference
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent resolves this contradiction by using vertical layering. The readout line and reset voltage wiring share the same layer, reducing horizontal routing complexity. However, the data line is positioned in a different layer, utilizing the vertical dimension to separate potentially interfering conductors. This multi-layer approach maintains simplicity where possible while applying dimensional separation where interference occurs.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the reliability of the display device by minimizing coupling capacitance, thereby improving the performance and functionality of integrated light-sensing pixels.

Implementation Method 1

a light-receiving element; a first sensor transistor for controlling current flowing to the readout line in response to a voltage of one electrode of the light-receiving element

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Data Source

PatentEP4672930A1Display device and electronic device including the same
Publication Date: 2025.12.31 SAMSUNG DISPLAY CO LTD
  • EP4672930A1 patent drawingFigure 1
  • EP4672930A1 patent drawingFigure 2
  • EP4672930A1 patent drawingFigure 3

AI summary

A display device includes: a first subpixel, a second subpixel, and a third subpixel arranged in a first direction; a light-sensing pixel including a sensor circuit, and disposed between the second subpixel and the third subpixel; a readout line extending along a second direction, and electrically connected to the light-sensing pixel; a first data line extending along the second direction, and electrically connected to the second subpixel; a second data line extending along the second direction, and electrically connected to the third subpixel; a dummy pattern disposed between the first data line and the second data line; and a reset voltage wiring electrically connected to the light-sensing pixel and supplied with a reset voltage. The readout line may be disposed in a different layer from the first and second data lines. The readout line may be disposed in a same layer as the reset voltage wiring.