Display Device Pixel Circuit with Self-Scan Flicker Stabilization
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Solution Overview
Problem
Display devices experience issues such as tearing and stuttering due to mismatched frame rates between the GPU rendering speed and panel-driving frames, leading to flicker and hysteresis characteristics in the display panel, which can be exacerbated by varying frame rates in real-time display operations.
Innovation Solution
A display device design incorporating specific transistor configurations, including n-type transistors, to minimize leakage current and reduce power consumption while improving image quality by stabilizing transistor characteristics and reducing flicker.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the frame rate of the panel-driving frame is decreased to synchronize with GPU rendering speed, then image quality improves by reducing tearing and stuttering, but power consumption increases due to extended driving time and transistor hysteresis effects
Solution Approach 1:
The patent implements dynamic frame rate adjustment by varying the vertical blank section duration based on GPU rendering speed requirements. This allows the panel-driving frame rate to adaptively synchronize with the source device, resolving tearing and stuttering issues while maintaining efficient power consumption through optimized driving time management.
Solution Approach 2:
The patent changes the vertical blank section parameter to control frame rate synchronization. By adjusting this timing parameter, the system achieves frame rate matching between the panel and GPU, improving image quality without excessive power consumption penalties.
2Reliability
If the vertical blank section is increased to lower the panel-driving frame rate, then frame rate synchronization improves, but flicker occurs due to fixed transistor characteristics during extended driving time
Solution Approach 1:
The patent introduces a self-scan segment that operates before the display scan segment to pre-initialize transistor characteristics. This preliminary action resets transistor states to predetermined values, preventing hysteresis-induced flicker during the subsequent display scanning at varied frame rates.
Solution Approach 2:
The self-scan segment acts as an intermediary process between frame rate adjustment and transistor stability. It mediates the effect of extended driving time by periodically resetting transistor characteristics, thereby maintaining stability despite variable frame rates required for synchronization.
3Adaptability or versatility
If real-time frame rate variation is implemented to match GPU rendering speed, then image synchronization improves, but transistor hysteresis effects are exacerbated causing display flicker
Solution Approach 1:
The patent implements periodic self-scan segments interspersed within the display scan segments. These periodic reset operations stabilize transistor characteristics at regular intervals, counteracting the destabilizing effect of real-time frame rate variations while maintaining the adaptability needed for GPU synchronization.
Solution Approach 2:
By performing transistor initialization in the self-scan segment before each display scan segment, the patent prepares the transistor characteristics in advance. This preliminary stabilization allows the subsequent display scanning to proceed with reduced hysteresis effects, even when frame rates are dynamically adjusted.
Data Source
AI summary
The present disclosure relates to a display device capable of improving image quality while reducing power consumption. According to one or more embodiments of the disclosure, a display device includes a light-emitting element connected between a driving voltage line and a common voltage line, a first transistor connected between the driving voltage line and the light-emitting element, a second transistor connected between a data line and a source electrode of the first transistor, a third transistor connected between a gate electrode of the first transistor and a drain electrode of the first transistor, and a fourth transistor connected between a drain electrode of the first transistor and a first initialization voltage line, wherein the third transistor and the fourth transistor include a same type.