Display Substrate Pixel Circuit Layout for High-Density Panels
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Solution Overview
Problem
The challenge of achieving high pixel density in display substrates is compounded by the limited layout space available for sub-pixels, leading to difficulties in designing high-resolution displays.
Innovation Solution
The display substrate design incorporates a specific arrangement of transistors and conductive connections, utilizing vertical and horizontal layout spaces efficiently, including a shielding pattern and power line to stabilize voltage and reduce interference, thereby optimizing the layout for high pixel resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel density is increased to improve display definition, then display quality is improved, but layout space for sub-pixels becomes limited
Solution Approach 1:
The patent applies multi-layer stacking to arrange transistor components vertically across different layers (first, second, and third layers), transforming a two-dimensional layout constraint into a three-dimensional arrangement. This allows more components to be packed into the same planar area by utilizing the vertical dimension, thereby supporting higher pixel density without increasing the overall display area.
Solution Approach 2:
The patent implements nested arrangement where the first transistor and second transistor are positioned within the same sub-pixel area but at different vertical levels. The first transistor occupies a lower layer while the second transistor is placed in an upper layer, creating a nested structure that maximizes space utilization. This nesting approach enables multiple functional elements to coexist in a compact footprint, addressing the layout space constraint.
2Ease of manufacture
If transistors are arranged to maximize space utilization, then layout difficulty is reduced, but signal interference increases
Solution Approach 1:
The patent introduces a shielding pattern as an intermediary element positioned between the first transistor and the second transistor. This shielding structure acts as a mediator that blocks electromagnetic interference between the closely spaced transistors while allowing the layout to remain compact. The shielding pattern enables tight packing for ease of manufacture while preventing harmful signal coupling.
Solution Approach 2:
The patent extracts and isolates the shielding function from the transistor structures themselves, creating a dedicated shielding pattern that is separate from the active transistor components. This extracted shielding element can be independently positioned and optimized to block interference without affecting the transistor operation, thereby solving the interference problem while maintaining layout efficiency.
Data Source
AI summary
A display substrate includes: a base substrate and a plurality of sub-pixels arranged on the base substrate, the sub-pixel include a sub-pixel driving circuit, the sub-pixel driving circuit includes: a first transistor, a driving transistor, and a first conductive connection portion; a first electrode of the first transistor is coupled to a second electrode of the driving transistor, a second electrode of the first transistor and a first end portion of the first conductive connection portion are arranged at different layers, the second electrode of the first transistor and the first end portion of the first conductive connection portion are coupled through a via hole; a second end portion of the first conductive connection portion is coupled to a gate electrode of the driving transistor.