Display Panel Pixel Circuit Layout for Signal Interference Reduction
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Solution Overview
Problem
Existing display technologies face challenges in achieving high-resolution displays with efficient power usage, managing signal interference, and maintaining device reliability, particularly in compact form factors.
Innovation Solution
A display panel design incorporating a pixel circuit with dual-gate driving transistors, oxide semiconductor materials, and symmetrical capacitor arrangements to minimize power loss and optimize signal transmission, using flexible and rigid components for diverse applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If electronic components are integrated into increasingly compact spaces to achieve high-resolution displays, then display resolution is improved, but signal interference increases and device reliability deteriorates
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar 2D conductor layouts to 3D vertically-stacked conductor patterns. Multiple conductive patterns are arranged at different heights (first, second, third, and fourth conductive patterns at different levels), allowing signals to be routed in the vertical dimension. This reduces horizontal spacing requirements and minimizes signal interference while maintaining compact footprint, thereby improving both resolution and reliability simultaneously.
Solution Approach 2:
The patent segments the conductor system into multiple distinct conductive patterns (first, second, third, and fourth conductive patterns) with different materials and vertical positions. Each pattern serves specific signal routing functions, separating power, ground, and data signals into different spatial zones. This segmentation reduces electromagnetic interference between signals while maintaining high integration density for high-resolution displays.
2Measurement precision
If electronic components are integrated into increasingly compact spaces to achieve high-resolution displays, then display resolution is improved, but signal interference increases
Solution Approach 1:
The patent utilizes vertical stacking of conductive patterns at different heights to route signals in three dimensions. This spatial separation in the vertical dimension reduces electromagnetic coupling between adjacent conductors compared to traditional planar layouts, thereby minimizing signal interference while achieving high-resolution display requirements through compact integration.
Solution Approach 2:
The patent introduces insulating layers and dielectric materials as intermediaries between different conductive patterns. These intermediary layers electrically isolate adjacent conductors, preventing signal interference and crosstalk while allowing dense integration of conductive elements necessary for high-resolution displays.
3Ease of manufacture
If conventional conductor patterns are used in compact spaces, then manufacturing is simpler, but power loss increases and energy efficiency deteriorates
Solution Approach 1:
The patent changes the material parameter of conductive patterns by using different materials for different conductive layers (e.g., first conductive pattern with one material, second conductive pattern with another material). This material differentiation optimizes electrical properties such as conductivity and resistance for specific signal types, reducing power loss while maintaining manufacturability through established multi-layer deposition techniques.
Data Source
AI summary
A display panel includes a first pixel circuit including a first conductive pattern disposed on the substrate, a second conductive pattern disposed on the first conductive pattern and overlapping the first conductive pattern, a first semiconductor pattern disposed on the second conductive pattern, the first semiconductor pattern including a semiconductor layer of the driving transistor, a second semiconductor pattern disposed on a same layer as the first semiconductor pattern and spaced apart from the first semiconductor pattern, and a third conductive pattern disposed on the first semiconductor pattern and connecting the first semiconductor pattern to the second conductive pattern, wherein the first conductive pattern is electrically connected to the second semiconductor pattern, and a portion of the second semiconductor pattern overlaps a hold gate line extending in a first direction and electrically connected to the first pixel circuit.