Display Pixel Line Layout for Lower Readout Coupling Capacitance
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Solution Overview
Problem
Existing display devices face challenges in achieving improved reliability and efficiency in integrating light-sensing pixels with sub-pixels, particularly in terms of reducing coupling capacitance and optimizing signal transmission.
Innovation Solution
The display device incorporates a specific layout of data lines, readout lines, and reset lines, including a readout line positioned closer to one data line in one pixel row and further from the other, with overlapping bridge lines to shield capacitance, and a layered structure of conductive layers to enhance signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the readout line is positioned between the first data line and the second data line in plan view, then the integration of light-sensing pixels with sub-pixels is improved, but coupling capacitance increases
Solution Approach 1:
The patent applies asymmetry by positioning the readout line closer to the second data line in odd pixel rows and closer to the first data line in even pixel rows. This asymmetric alternating pattern reduces the average coupling capacitance between the readout line and data lines while maintaining functional integration, resolving the contradiction between integration reliability and capacitance reduction.
Solution Approach 2:
The patent introduces a vertical dimension to the line arrangement by using multiple conductive layers. The readout line is positioned in a different conductive layer than the data lines, allowing spatial separation in the vertical dimension while maintaining planar proximity for functional integration. This layered approach reduces coupling capacitance by increasing physical distance between conductors.
2Object-generated harmful factors
If overlapping bridge lines are used to shield capacitance, then coupling capacitance is reduced, but device complexity increases
Solution Approach 1:
The patent uses bridge lines as intermediary conductive structures that connect data lines across pixel rows. These bridge lines are strategically positioned to shield the readout line from capacitive coupling with data lines by acting as electromagnetic shields. The bridge lines mediate between the need for simple line structures and the requirement to reduce coupling capacitance.
Solution Approach 2:
The patent resolves the complexity issue by implementing the shielding function in the vertical dimension through multiple conductive layers. Rather than creating complex planar patterns, the shield bridge lines are placed in upper conductive layers above the readout line, providing capacitance shielding through vertical spatial separation while maintaining a relatively simple overall structure.
3Reliability
If multiple conductive layers are used to enhance signal integrity, then signal transmission efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent uses multiple conductive layers arranged in the vertical dimension to separate different signal paths. The readout line is in a different conductive layer than the data lines, which reduces capacitive coupling and enhances signal integrity. This vertical layering approach maintains manufacturing simplicity by using standard multi-layer PCB or thin-film fabrication techniques rather than requiring complex three-dimensional structures.
Solution Approach 2:
The patent introduces insulating layers as intermediary materials between conductive layers. These insulating layers mediate the electrical isolation between different conductive planes, enabling enhanced signal transmission through reduced interference while maintaining ease of manufacture through conventional lamination or deposition processes used in multi-layer conductor fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces coupling capacitance and improves signal transmission efficiency, enhancing the reliability and performance of the display device by optimizing the integration of light-sensing pixels with sub-pixels.
Implementation Method 1
The first sub-line may be configured to shield a coupling capacitance between the horizontal bridge line and the readout line in the overlap area.
Data Source
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AI summary
A display device according to one or more embodiments may include a substrate, first sub-pixels, second sub-pixels, and third sub-pixels respectively arranged in a first pixel row and a second pixel row extending in a first direction, light-sensing pixels between respective ones of the second sub-pixels and the third sub-pixels in the first pixel row and the second pixel row, and including a sensor circuit, a first data line electrically connected to the second sub-pixels, a second data line electrically connected to the third sub-pixels, and a readout line electrically connected to the light-sensing pixels, between the first data line and the second data line in plan view, adjacent to one of the first data line or the second data line in the first pixel row, and adjacent to a remaining one of the first data line or the second data line in the second pixel row.