Display Pixel Circuit Layout Using Oxide and Polycrystalline TFTs
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Solution Overview
Problem
Organic light emitting devices face issues with increased number of pixels leading to reduced aperture ratio, high current density, and deteriorated transistor reliability due to high driving voltage, resulting in stability and power consumption challenges.
Innovation Solution
A display device design incorporating polycrystalline silicon semiconductors for driving transistors and oxide semiconductors for other transistors, with specific electrode and initialization voltage line configurations, including overlapping initialization voltage lines and connection electrodes on different layers, to stabilize operation and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels is increased to increase resolution, then the resolution is improved, but the aperture ratio is reduced
Solution Approach 1:
The patent applies dimensionality change by stacking multiple transistor layers (first through fourth transistors) vertically within the pixel structure. This multi-layer configuration allows more functional elements to be integrated without increasing the planar footprint, thereby maintaining a higher aperture ratio while supporting increased pixel density for improved resolution.
Solution Approach 2:
The patent implements nesting by placing multiple transistor layers and capacitor structures within each other in the vertical dimension. The first and second transistors are formed in a first layer, while the third and fourth transistors are formed in a second layer above it, with interlayer insulating layers separating them. This nested arrangement maximizes space utilization within the pixel area.
2Reliability
If the driving voltage is increased to improve transistor performance, then the transistor performance is improved, but the reliability is deteriorated
Solution Approach 1:
The patent employs parameter changes by utilizing different semiconductor material types for different transistor functions. Oxide semiconductor transistors (third and fourth transistors) are used for switching functions requiring low off-state current and high stability, while polycrystalline semiconductor transistors (first and second transistors) are used for driving functions requiring high current capability. This material parameter differentiation allows optimized performance at lower voltages, reducing stress and stain generation.
Solution Approach 2:
The patent applies composite materials by combining oxide semiconductor and polycrystalline semiconductor in the same display device. Each material type is strategically assigned to specific transistor roles based on their electrical characteristics, creating a composite system that achieves both high reliability and low stain generation without requiring excessive driving voltage.
3Power
If the current density is increased to improve driving capability, then the driving capability is improved, but the reliability is deteriorated
Solution Approach 1:
The patent applies local quality by assigning different semiconductor material properties to different locations (transistors) within the pixel circuit based on their specific functional requirements. The oxide semiconductor transistors provide low off-state current for stable voltage holding, while polycrystalline semiconductor transistors provide high on-state current for driving capability. This localized optimization of material properties enables high driving capability without compromising reliability in critical areas.
Data Source
AI summary
A display device includes a substrate, a polycrystalline semiconductor layer including a channel of a driving transistor, and a channel of a seventh transistor, a gate electrode of the driving transistor overlapping the channel thereof, a gate electrode of the seventh transistor overlapping the channel thereof, an oxide semiconductor layer including a channel of a fourth transistor, a gate electrode thereof overlapping the channel of the fourth transistor, a first initialization voltage line connected to a first electrode of the fourth transistor, the first initialization voltage line and the gate electrode of the fourth transistor being position on a same layer, and a second initialization voltage line connected to a second electrode of the seventh transistor, the second initialization voltage line and the first initialization voltage line being positioned on different layers from each other.