Display Panel Pixel Circuit With Stacked Capacitor for Gate Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current display technologies face challenges in optimizing the structure and efficiency of pixel circuits in display panels, particularly in achieving stable gate voltage and reducing leakage currents, which affect the performance and stability of electroluminescent diodes like OLED and QLED.
Innovation Solution
The display panel incorporates a pixel circuit with a silicon semiconductor layer, oxide semiconductor layer, and specific transistor configurations, including initialization and threshold compensation transistors, to enhance the stability of the gate voltage and reduce leakage currents by using shared electrode areas and double-gate transistors, and a storage capacitor with stacked electrode plates to increase capacitance without area expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional pixel circuit structure is used, then the device complexity is lower, but the gate voltage stability deteriorates and leakage currents increase
Solution Approach 1:
The patent merges the gate electrode of the driving transistor with one electrode plate of the storage capacitor to form a shared conductive structure. This integration reduces the number of separate components while maintaining both the voltage stability function of the storage capacitor and the transistor control function, thereby improving reliability without proportionally increasing device complexity
Solution Approach 2:
The patent introduces a stacked three-dimensional structure where the storage capacitor is formed with electrode plates at different vertical levels. The gate electrode of the driving transistor is positioned at a different height and electrically connected to one of the capacitor's electrode plates, utilizing the vertical dimension to achieve both functions within a compact space, thus improving gate voltage stability without significantly increasing planar area
2Reliability
If the storage capacitor area is increased to improve capacitance, then the gate voltage stability improves, but the pixel area increases
Solution Approach 1:
The storage capacitor is constructed with electrode plates stacked in the vertical direction rather than extending in the planar direction. This three-dimensional configuration increases the capacitance value (C = εA/d, where increasing plate separation d in a controlled manner or adding stacked plates effectively increases capacitance) while maintaining a compact pixel footprint, thus improving gate voltage stability without expanding pixel area
Solution Approach 2:
The storage capacitor structure is integrated with the driving transistor gate electrode, where they share common conductive regions and insulating layers. This merging allows the capacitor to utilize the same vertical space as the transistor structure, increasing capacitance without requiring additional pixel area
3Reliability
If more transistor components are added for threshold compensation, then the gate voltage stability improves, but the device complexity increases
Solution Approach 1:
The threshold compensation transistor is integrated with the driving transistor such that they share common structural elements including the gate electrode, source/drain regions, and insulating layers. This merged configuration implements threshold compensation functionality while reducing the number of discrete components, thereby improving gate voltage stability without proportionally increasing device complexity
Solution Approach 2:
The shared gate electrode structure serves multiple functions: it acts as the control electrode for the driving transistor, one electrode plate of the storage capacitor, and the control electrode for the threshold compensation transistor. This multi-functionality allows comprehensive voltage stability control through a unified structure, improving reliability while minimizing device complexity
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
The embodiments of the disclosure disclose a display panel and a display device. The display panel includes a base substrate including a plurality of sub-pixels, at least one of the plurality of sub-pixels including a pixel circuit, wherein the pixel circuit includes a storage capacitor; a first conductive layer located on a side, facing away from the base substrate, of a first insulating layer, the first conductive layer including a plurality of scanning wires; a second insulating layer located on a side, facing away from the base substrate, of the first conductive layer; a second conductive layer located on a side, facing away from the base substrate, of the second insulating layer; a fourth insulating layer located on a side, facing away from the base substrate, of the second conductive layer; and a third conductive layer located on a side, facing away from the base substrate, of the fourth insulating layer, the third conductive layer including a plurality of data wires arranged at intervals; where the storage capacitor includes three stacked electrode plates, and the three stacked electrode plates are respectively arranged on the same layer together with the first conductive layer, the second conductive layer and the third conductive layer.