Display Pixel Circuit Layout Using Stacked Semiconductor Layers
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Solution Overview
Problem
There is a demand for compact and high-resolution display devices with efficient space arrangement, connection structures, and improved image quality, particularly in thin film transistors and capacitors.
Innovation Solution
A display device design incorporating a light emitting element, transistors with channels in different semiconductor layers, and capacitors arranged to enhance resolution, including specific transistor and capacitor configurations and conductive layers for improved signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If all transistor channels are placed in a single semiconductor layer, then the connection structure is simple, but the space arrangement efficiency and resolution are insufficient
Solution Approach 1:
The patent transitions from a single-layer semiconductor structure to a multi-layer semiconductor structure. Specifically, it uses a first semiconductor layer for the first transistor channel and a second semiconductor layer for the second transistor channel, utilizing the vertical dimension to achieve better space arrangement and improved resolution while maintaining manageable complexity through systematic layer organization
2Area of stationary object
If capacitors are arranged to overlap transistor channels, then space utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements nesting by positioning the first capacitor to overlap with the first transistor channel in the first semiconductor layer, and the second capacitor to overlap with the second transistor channel in the second semiconductor layer. This nested arrangement maximizes space utilization by having capacitors and transistors occupy the same horizontal footprint while being separated vertically through different semiconductor layers, thereby reducing manufacturing precision requirements compared to planar overlap
Data Source
AI summary
A display device includes a light emitting element, a first transistor which applies a driving current to the light emitting element, a first capacitor including a first electrode connected to a gate electrode of the first transistor and a second electrode, a second transistor which applies a data voltage to the second electrode of the first capacitor in response to a write gate signal, a third transistor which diode-connects the first transistor in response to a compensation gate signal, and a fourth transistor which applies an initialization voltage to an anode of the light emitting element in response to an initialization gate signal. A channel of the first transistor and a channel of the third transistor are in a first semiconductor layer. A channel of the second transistor and a channel of the fourth transistor are in a second semiconductor layer arranged on the first semiconductor layer.