Display Pixel Wiring Layout for Compensation Time and Crosstalk Control
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Solution Overview
Problem
Existing display devices face challenges in ensuring sufficient time for compensating for threshold voltage and storing data signals while overcoming spatial limitations.
Innovation Solution
A display apparatus with a pixel structure that includes two data lines per pixel, a capacitor overlapping the data lines, and a driving voltage line with specific overlapping regions to prevent parasitic capacitance, allowing for sufficient time for threshold voltage compensation and data signal storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If two data lines are arranged in one pixel, then the time for threshold voltage compensation and data signal storage is sufficient, but the spatial area occupied by wiring increases
Solution Approach 1:
The patent transitions from a planar arrangement to a three-dimensional stacked structure by placing the first and second data lines on different layers (first and second insulating layers). This vertical stacking allows two data lines to be accommodated within the same horizontal pixel area, effectively utilizing the third dimension (depth/layer) to resolve the spatial conflict while maintaining sufficient time for voltage compensation and data storage.
Solution Approach 2:
The patent implements a nested structure where the first data line is embedded in the first insulating layer and the second data line is embedded in the second insulating layer that covers the first layer. This nested arrangement allows the data lines to be contained within each other's vertical space, maximizing space utilization while providing adequate temporal characteristics for pixel operation.
2Device complexity
If data lines are arranged on the same layer, then the structure is simple, but crosstalk between adjacent data lines occurs due to same-polarity signals
Solution Approach 1:
The patent eliminates crosstalk by separating the first and second data lines into different vertical layers (first and second insulating layers). This spatial separation in the vertical dimension prevents electromagnetic coupling between adjacent data lines carrying same-polarity signals, effectively eliminating crosstalk while maintaining reasonable structural complexity through systematic layering.
Solution Approach 2:
The patent introduces insulating layers as intermediary structures between the data lines. The first insulating layer contains the first data line, and the second insulating layer contains the second data line, with the second layer acting as an electromagnetic shield between the two data lines. This intermediary insulation prevents direct electromagnetic interaction and crosstalk between adjacent data lines.
3Object-generated harmful factors
If the driving voltage line does not overlap the data lines, then parasitic capacitance is reduced, but the area required for voltage line routing increases
Solution Approach 1:
The patent resolves the conflict by placing the driving voltage line in the second insulating layer, which vertically overlaps with the first data line in the first insulating layer. This vertical stacking allows the voltage line to be routed through the same horizontal area as the data lines without creating parasitic capacitance, as the insulating layers provide electrical isolation. The third dimension (vertical layering) enables space-efficient routing while maintaining low parasitic capacitance.
Data Source
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AI summary
A display apparatus includes a first transistor, a first data line, a second data line, a driving voltage line, and a first insulating layer. The first transistor includes a first semiconductor layer and a first gate electrode. The first semiconductor layer includes a source region and a drain region. The first data line is disposed at a left side of the first transistor, and the second data line is disposed at a right side of the first transistor. The driving voltage line at least partially overlaps the first data line and the second data line. The first insulating layer is disposed between the first data line and the driving voltage line and between the second data line and the driving voltage line.