Display Data Communication Using PLL Clock Recovery
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Solution Overview
Problem
Existing liquid crystal display devices suffer from reduced communication efficiency due to the addition of clock bits in video data signals, which increases data transmission overhead.
Innovation Solution
A data communication system that includes a transmission circuit with an encoder adding or subtracting a value to the information data piece and a reception circuit with a PLL circuit synchronized to the rising or falling edge of the data signal, eliminating the need for additional clock bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock bits are added to video data signal for synchronization, then data transmission reliability is improved, but communication efficiency deteriorates due to increased data transmission overhead
Solution Approach 1:
The invention extracts the clock signal generation function from the transmitted data stream by utilizing the inherent transition edges of the data signal itself. Instead of adding separate clock bits, the system extracts timing information directly from the data signal's rising and falling edges, thereby removing the overhead while maintaining synchronization capability.
Solution Approach 2:
The data signal serves dual purposes: it carries both the information data and the clock synchronization signal. The transition edges of the data signal are utilized for both data transmission and timing reference, allowing one signal to fulfill multiple functions and eliminating the need for separate clock bits.
2Measurement precision
If additional clock bits are transmitted for phase synchronization, then timing accuracy is improved, but data transmission speed deteriorates due to increased overhead
Solution Approach 1:
The data signal itself provides the timing reference needed for synchronization. The transition edges inherent in the data signal are used to generate the clock signal, making the system self-sufficient and eliminating the need for external or additional timing information.
Solution Approach 2:
The invention changes the parameter used for clock generation from dedicated clock bits to the transition edge characteristics of the data signal. By utilizing the existing signal's temporal characteristics rather than adding separate timing parameters, the system maintains timing accuracy without increasing overhead.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves communication efficiency by generating a clock signal without additional clock bits, enhancing data transmission performance.
Implementation Method 1
a PLL circuit that receives the information data signal and generates a clock signal that is phase-synchronized with a rising edge or a falling edge of the information data signal
Data Source
AI summary
A data communication system includes a transmission circuit including an encoder that receives an information data piece composed of N (N is an integer of 2 or greater) bits and generates a converted information data piece in a serial form composed of first to N-th bits representing a value, which is obtained by adding 1 to a value represented by the information data piece, and transmitting an information data signal including the converted information data piece, and a reception circuit including a PLL circuit that receives the information data signal and generates a clock signal that is phase-synchronized with a rising edge or a falling edge of the information data signal, and a decoder that receives the information data signal and subtracts 1 from the value represented by the information data piece included in the information data signal to restore the information data piece.