Display PLL Clock Recovery With LC VCO Tuning for Low Jitter
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Solution Overview
Problem
Existing phase-locked loops (PLLs) in displays have high sensitivity to supply voltage and noise, making them unsuitable for low-jitter applications due to their reliance on ring oscillators and voltage-controlled oscillators (VCOs), which are sensitive to parasitic capacitance and require multiple LC VCOs for adequate frequency tuning.
Innovation Solution
A timing controller using a PLL with a VCO selector and an LC resonant circuit, including fixed capacitors and a varactor, performs coarse and fine frequency tuning to generate a clock, selecting the appropriate VCO based on the input clock frequency to achieve a wide frequency range with reduced jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a ring oscillator is used for clock generation, then the frequency can be adjusted by changing current or voltage swing, but the PLL has high sensitivity to supply voltage and the VCO has high noise, resulting in high jitter
Solution Approach 1:
The oscillator is divided into multiple delay cells connected in series, where each cell contributes a specific delay. By selectively enabling or disabling certain delay cells, the total delay and thus the frequency can be adjusted without changing current or voltage swing magnitudes, reducing noise and jitter while maintaining frequency adjustability
Solution Approach 2:
Instead of changing current or voltage swing to adjust frequency, the invention changes the effective delay by selectively connecting or disconnecting delay cells. This parameter change approach allows frequency adjustment while maintaining stable supply voltage and reducing VCO noise, thereby improving jitter characteristics
2Adaptability or versatility
If the controllable capacitor to parasitic capacitance ratio is increased to expand frequency tuning range, then more capacitors are needed, but this increases device complexity and cost
Solution Approach 1:
The invention introduces a dynamic element (variable capacitor) that can change its capacitance value based on control signals. This dynamic capacitance adjustment allows the frequency tuning range to be expanded without proportionally increasing the number of fixed capacitors, reducing device complexity while maintaining adaptability
Solution Approach 2:
The variable capacitor's capacitance parameter is dynamically changed based on the input clock frequency to achieve wide frequency tuning. This approach provides frequency adaptability without requiring a large number of fixed capacitors, thereby reducing device complexity and cost
3Adaptability or versatility
If multiple LC VCOs are used to achieve a frequency ratio of 2 or more, then the frequency range is sufficient, but the device complexity and cost increase significantly
Solution Approach 1:
The invention makes a single VCO multi-functional by enabling it to operate across a wide frequency range through dynamic capacitance adjustment. This single VCO replaces multiple LC VCOs, achieving the same frequency coverage while significantly reducing device complexity and cost
Solution Approach 2:
The variable capacitor allows the single VCO to dynamically change its resonant frequency parameter, enabling it to cover a frequency range that would otherwise require multiple VCOs. This parameter change capability provides wide frequency adaptation with minimal device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables a timing controller to generate a clock with improved jitter characteristics, supporting high-speed interfaces by selecting the appropriate VCO and tuning the LC resonant circuit to match the input clock frequency, thereby reducing noise and increasing the frequency range.
Implementation Method 1
an LC resonant circuit connected with the selected VCO, including a plurality of fixed capacitors, and configured to perform coarse frequency tuning of the selected VCO
Implementation Method 2
an LC resonant circuit including a plurality of fixed capacitors and a varactor, connected with the selected VCO, and configured to perform coarse frequency tuning and fine frequency tuning of the selected VCO
Data Source
AI summary
Provided are a phase-locked loop (PLL) receiving an input clock and generating a clock, a display using the PLL, and a method for a timing controller to generate a clock using the PLL. The display includes a timing controller configured to generate a first clock using a PLL, insert the first clock into data, and transmit the data into which the first clock is inserted, transmission lines configured to transfer the data into which the first clock is inserted, and data-driver integrated circuits (ICs) configured to receive the data into which the first clock is inserted, separate the first clock from the data, and drive data lines of a liquid crystal panel on the basis of the first clock and the data. The PLL includes a phase detector configured to generate a DC error corresponding to a phase difference between an input clock and the first clock, a plurality of voltage-controlled oscillators (VCOs), a VCO selector configured to select a VCO having a frequency operating range, which is a range from the highest oscillation frequency of the VCO to the lowest oscillation frequency, including a frequency of the first clock from among the plurality of VCOs with reference to the DC error, and an inductor/capacitor (LC) resonant circuit connected with the selected VCO, including a plurality of fixed capacitors, and configured to perform coarse frequency tuning of the selected VCO.