Display Data Training Signals for PLL-Based High-Speed Links
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Solution Overview
Problem
Existing display devices face challenges in high-speed data communication due to increased pixel count and frame rates, leading to limitations in data transmission efficiency, particularly when using delay locked loops (DLL) for data restoration.
Innovation Solution
Configuring unique patterns for clock and blank training signals to facilitate high-speed data communication by employing phase locked loops (PLL) circuits, ensuring guaranteed loop bandwidth and improved jitter tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DLL circuits are used for data restoration in high-resolution display devices, then data transmission can be maintained, but data communication speed and jitter tolerance are limited
Solution Approach 1:
The patent changes the circuit type parameter from DLL to PLL, which fundamentally alters the frequency multiplication mechanism and phase detection capabilities, enabling both higher data communication speeds and improved jitter tolerance simultaneously
Solution Approach 2:
The patent introduces a preliminary clock training phase before data transmission, where the PLL circuit is pre-configured and locked to the incoming clock signal, ensuring optimal performance is established in advance for subsequent high-speed data communication
2Measurement precision
If the number of pixels and frame rate are increased to improve display resolution, then image quality is improved, but the amount of image data increases leading to communication bottlenecks
Solution Approach 1:
The patent employs dynamic frequency multiplication through PLL, allowing the system to adaptively handle varying data rates required by different resolutions and frame rates, maintaining optimal data transmission efficiency across different display configurations
Solution Approach 2:
The PLL-based training signal generation circuit serves multiple functions: it generates clock training signals for PLL locking, generates blank training signals for data alignment, and maintains synchronization across different data rates, replacing multiple dedicated circuits with a single multi-functional solution
Data Source
AI summary
A technology for transmitting a training signal with a pattern that enables high-speed data transmission in a training process performed before transmission of video data is disclosed. A method of receiving data in a display driving device according to one of the various embodiments of the present disclosure can include receiving a first training signal transmitted from a display processing device; generating a clock signal based on the first training signal; confirming a second training signal transmitted from the display processing device based on the generated clock signal; and confirming data transmitted from the display processing device based on the second training signal.