Display Port Clock Recovery via Phase Locking
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Solution Overview
Problem
Existing display port interfaces face challenges in efficiently managing frequency selection and clock recovery for multiple display technologies, leading to issues like screen tearing during wake-up and synchronization, especially when transitioning between different power modes.
Innovation Solution
A system where a source processor selects a frequency from a continuous range and transmits data to a sink processor, which includes a phase locking circuit to generate a signal in phase with the data, enabling clock recovery and sampling of transmitted data, thereby maintaining synchronization across different display modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a display port interface uses fixed clock frequencies for different display technologies, then compatibility with legacy displays is improved, but flexibility in optimizing power consumption and performance is reduced
Solution Approach 1:
The patent implements dynamic clock frequency adjustment by allowing the source processor to select from a continuous range of frequencies rather than being constrained to fixed frequencies. The system dynamically trains the link at different frequencies and allows the sink processor to recover and lock onto the selected frequency, enabling optimization of power consumption and performance based on display requirements while maintaining compatibility through the training sequence mechanism
Solution Approach 2:
The patent changes the clock frequency parameter from discrete fixed values to a continuous selectable range. The source processor can select any frequency within the supported range, and the system adapts by training the link at that frequency. This parameter change enables fine-grained optimization of power consumption and performance while the training sequence ensures compatibility with various display technologies
2Adaptability or versatility
If the interface supports multiple display technologies with different frequency requirements, then versatility is improved, but synchronization issues like screen tearing during wake-up occur
Solution Approach 1:
The patent applies preliminary action by implementing a training sequence before data transmission begins. The source processor transmits training patterns at the selected frequency, allowing the sink processor's phase locking circuit to acquire and lock onto the frequency before actual display data is transmitted. This preliminary frequency acquisition ensures synchronization stability when transitioning between different display technologies and power modes
Solution Approach 2:
The patent implements feedback through the phase locking circuit in the sink processor, which continuously monitors the received signal and adjusts its internal clock recovery to maintain lock with the transmitted frequency. This feedback mechanism ensures stable synchronization across different display technologies and prevents issues like screen tearing during wake-up transitions
3Ease of manufacture
If the interface uses traditional frequency selection methods, then ease of implementation is improved, but clock recovery accuracy and phase synchronization deteriorate
Solution Approach 1:
The patent replaces traditional mechanical or fixed-frequency clock distribution with an electronic phase locking system. Instead of using separate clock signals for different frequencies, the system uses a single continuous frequency source with the sink processor electronically locking onto the selected frequency through phase detection and adjustment. This substitution maintains implementation simplicity while significantly improving clock recovery accuracy and phase synchronization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures seamless frequency adjustment and synchronization, reducing screen tearing and power consumption, and supporting multiple display technologies through efficient clock recovery and phase locking mechanisms.
Implementation Method 1
The sink processor may include a phase locking circuit which may generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.
Implementation Method 2
The sink processor may be configured to recover a clock from the transmitted data. The recovered clock may be dependent upon the signal generated by the phase locking circuit.
Data Source
AI summary
Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.