Display Port Link Clock Change During Vertical Blanking

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Solution Overview

Problem

Existing display port interfaces face challenges in efficiently managing power consumption and synchronization between processors and displays, particularly during transitions between sleep and active modes, leading to issues like display tearing and inefficient power usage.

Innovation Solution

The implementation of a display port interface with a primary link and an auxiliary link, where the source processor sends a wake-up command and initialization parameters, including clock data recovery parameters, to the sink processor, allowing for efficient clock recovery and synchronization, and enabling reduced power operation modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the display port interface operates in sleep mode to reduce power consumption, then power efficiency is improved, but synchronization between processor and display may be lost causing display tearing

Engineering Contradiction:

Improvepower consumptionVSAvoidsynchronization

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by sending initialization parameters including clock data recovery parameters and idle period parameters before the actual sleep mode transition. This ensures that when the display wakes up, all synchronization parameters are already prepared and configured, preventing display tearing during mode transitions while maintaining power efficiency during sleep.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms through auxiliary links that allow the display to communicate status and requirements back to the processor. This feedback loop ensures that synchronization is maintained even during sleep mode transitions, as the display can signal when it needs specific clock recovery parameters or idle periods to maintain proper synchronization upon waking.

Inventive Principle:

Principle #23Feedback

2Reliability

If the interface transmits data continuously to maintain synchronization, then display synchronization is improved, but power consumption increases

Engineering Contradiction:

ImprovesynchronizationVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies periodic action by using idle periods within the data transmission stream to convey synchronization information. Instead of continuous data transmission, the interface uses periodic idle periods during vertical blanking or horizontal retrace to transmit clock data recovery parameters and synchronization information, reducing power consumption while maintaining display synchronization.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent introduces auxiliary links as intermediaries that handle synchronization communication separately from the main data transmission path. This allows the primary data link to enter low-power states while the auxiliary link maintains synchronization communication, enabling power savings without sacrificing synchronization reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Manufacturing precision

If the interface uses complex protocols to manage sleep and wake transitions, then transition accuracy is improved, but device complexity increases

Engineering Contradiction:

Improvetransition accuracyVSAvoidinterface complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges multiple synchronization functions into a single comprehensive initialization parameter transmission mechanism. By combining clock data recovery parameters, idle period parameters, and synchronization information into one coordinated transmission sequence during vertical blanking, the interface achieves accurate sleep-wake transitions without requiring multiple separate complex protocols.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements multi-functionality in the auxiliary link that can handle both data transmission and synchronization coordination. This universal interface component manages multiple functions including sending wake-up commands, transmitting initialization parameters, and maintaining synchronization, thereby reducing overall interface complexity while maintaining transition accuracy.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9158350B2Link clock change during veritcal blanking

Publication Date: 2015.10.13 APPLE INC

AI summary

Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.