Display Port Interface Synchronization During Vertical Blanking

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing display port interfaces face challenges in maintaining synchronization between processors and displays during vertical blanking periods, leading to issues like display tearing due to timing reference desynchronization.

Innovation Solution

The implementation of a display port interface with a primary link, an auxiliary link, and a hot plug detect link, where a source processor sends a wake-up command, synchronization signal, and sleep command to a sink processor, including parameters for clock data recovery and idle periods, to synchronize internal timing circuits and maintain vertical synchronization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the display port interface enters sleep mode during vertical blanking to save power, then energy consumption is reduced, but synchronization between source and sink processors deteriorates

Engineering Contradiction:

Improvepower consumptionVSAvoidsynchronization accuracy

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The source processor sends a wake-up command before the vertical blanking period begins, preparing the sink processor to maintain or restore its timing reference. This preliminary action ensures that when the display exits sleep mode, the synchronization is already re-established, preventing display tearing while allowing power savings during the actual blanking period.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The interface implements a feedback mechanism where the source processor monitors the display's sleep state and actively manages synchronization by sending wake-up commands and synchronization signals. This closed-loop control ensures that power management actions do not compromise synchronization, as the system continuously adjusts to maintain timing accuracy despite entering and exiting sleep modes.

Inventive Principle:

Principle #23Feedback

2Reliability

If the interface transmits data continuously to maintain synchronization, then synchronization accuracy is improved, but energy consumption increases

Engineering Contradiction:

Improvesynchronization accuracyVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

Instead of continuous data transmission, the interface uses periodic wake-up commands sent at specific intervals (before vertical blanking) and synchronization signals transmitted at defined moments. This periodic approach maintains synchronization accuracy by updating timing references only when necessary, rather than continuously, thereby reducing energy consumption during periods when full synchronization is not required.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent extracts the essential synchronization function from continuous data transmission by isolating and transmitting only the critical timing reference information during vertical blanking periods. This allows the system to maintain synchronization accuracy by sending minimal necessary data (wake-up commands and sync signals) rather than continuous video data, significantly reducing energy consumption while preserving synchronization.

Inventive Principle:

Principle #2Taking out (Extraction)

3Use of energy by moving object

If the sink processor maintains its internal timing reference independently during sleep mode, then power consumption is reduced, but timing desynchronization occurs

Engineering Contradiction:

Improvepower consumptionVSAvoidtiming reference accuracy

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The source processor sends a wake-up command before the vertical blanking period to alert the sink processor to prepare for potential timing updates. This preliminary notification allows the sink processor to maintain its internal timing reference with minimal power consumption during sleep mode while being ready to quickly resynchronize when the wake-up command is received, thus losing minimal timing accuracy.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The interface introduces an intermediary synchronization mechanism that mediates between the source processor's timing reference and the sink processor's internal clock. During sleep mode, the sink processor can operate independently with reduced power, but the intermediary sync signals sent during vertical blanking act as a mediator to realign timing references, preventing cumulative timing drift while minimizing power consumption.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9785184B2Maintaining synchronization during vertical blanking

Publication Date: 2017.10.10 APPLE INC

AI summary

Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, an auxiliary link, and a hot plug detect link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link. The source processor may send initialization parameters to the sink processor via the primary link. The initialization parameters may include a clock data recovery lock parameter and an idle parameter. Following the initialization parameters, the source processor may send a synchronization signal to the sink processor via the primary link. The source processor may then send a sleep command via the primary link to the sink processor.