Display Device Reception Circuit Power Management
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Solution Overview
Problem
Existing display devices consume power in digital logic circuits during low-speed operation, even in skip frames where sampling is not performed, leading to inefficiencies in power management.
Innovation Solution
A display device and method that activates the reception circuit during refresh frames and deactivates it during skip frames in Variable Refresh Rate (VRR) mode, reducing unnecessary logic operations and power consumption by maintaining the data voltage level from the last refresh frame.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reception circuit is kept active during skip frames to maintain readiness, then the device can quickly resume normal operation, but power consumption increases unnecessarily
Solution Approach 1:
The reception circuit dynamically changes its operational state based on the frame type. During refresh frames, the circuit is fully active to receive and process image data. During skip frames, the circuit is deactivated to save power. This dynamic adaptation resolves the contradiction by making the circuit reliable when needed and energy-efficient when not needed.
Solution Approach 2:
The reception circuit operates periodically rather than continuously. It activates during refresh frames and deactivates during skip frames, creating a periodic on-off pattern that aligns with the display's refresh cycle. This periodic operation maintains reliability during necessary periods while reducing power consumption during unnecessary periods.
2Reliability
If digital logic circuits operate continuously to handle potential data streams, then data processing reliability is maintained, but power consumption increases during low-speed operation
Solution Approach 1:
The operation of digital logic circuits is segmented into active periods (refresh frames) and inactive periods (skip frames). This segmentation allows the system to maintain full processing capability when needed while completely shutting down processing during periods when no data processing is required, thus resolving the contradiction between reliability and power consumption.
Solution Approach 2:
The operational parameter of the digital logic circuits changes from active to inactive state based on the frame type. This parameter change allows the system to adapt its power consumption level to the actual processing requirements, maintaining reliability when processing is needed and reducing power consumption when processing is not needed.
3Reliability
If sampling is performed in every frame to ensure image quality, then display quality is maintained, but power consumption and processing load increase
Solution Approach 1:
The sampling operation is extracted from the skip frame and performed only during refresh frames. This extraction eliminates unnecessary sampling operations during skip frames, reducing power consumption and processing load while maintaining image quality during refresh frames when sampling actually occurs.
Data Source
AI summary
A display device capable of maximizing power consumption reduction of a digital logic circuit during low-speed operation and a method for operating the same are disclosed. The display device includes a display panel; and a plurality of source drivers configured to convert image data into data voltage and provide the data voltage to the display panel, wherein each of the plurality of source drivers includes a reception circuit configured to reconstruct at least one of the image data, control data, and a clock from a data packet received from a timing controller, wherein in a variable refresh rate mode operation, the display device is configured to activate the reception circuit during a refresh frame and to deactivate the reception circuit during a skip frame.