Light Emitting Display Reference Line Configuration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Light emitting display apparatuses face signal delay and reduced charge rate due to parasitic capacitance caused by the overlap area between horizontal and vertical signal lines, leading to load and ripple issues, which degrade display quality and increase power consumption.
Innovation Solution
The apparatus is designed with a reduced overlap area between lines by configuring the reference lines to minimize parasitic capacitance, where a first subpixel group connects with a reference line and a second subpixel group connects with an adjacent different pixel's reference line, thereby decreasing the overlap area and enhancing charge rate and display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the horizontal signal line and vertical signal line overlap in the pixel circuit, then the connection between subpixels and reference lines is established, but parasitic capacitance increases causing signal delay and reduced charge rate
Solution Approach 1:
The patent extracts and removes the overlapping section of the horizontal signal line from the pixel circuit structure. By making the horizontal signal line extend outside the pixel circuit boundaries, the overlap with vertical signal lines is eliminated, thereby removing the source of parasitic capacitance while maintaining electrical connectivity.
Solution Approach 2:
The patent changes the spatial arrangement by extending the horizontal signal line to a different dimensional position (outside the pixel circuit area) rather than keeping it confined within the pixel circuit. This dimensional repositioning eliminates the overlap problem in the original two-dimensional plane.
2Ease of operation
If the overlap area between horizontal and vertical signal lines is large, then the lines are well-connected, but parasitic capacitance increases causing load and ripple issues
Solution Approach 1:
The harmful overlapping section is extracted and removed from the structure. The horizontal signal line is reconfigured to extend outside the pixel circuit, eliminating the parasitic capacitance-generating overlap while preserving the essential connection function through alternative routing.
3Productivity
If the overlap area between lines is reduced, then parasitic capacitance decreases improving charge rate, but the line connection structure becomes more complex
Solution Approach 1:
The signal line structure is segmented into distinct sections: the vertical signal line remains confined within the pixel circuit, while the horizontal signal line extends outside. This segmentation allows each line to be optimized independently, reducing parasitic capacitance without creating complex interconnections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces signal delay and parasitic capacitance, improving the charge rate and display quality while reducing power consumption, allowing the light emitting display apparatus to be driven with low power.
Implementation Method 1
Light emitting display apparatuses display an image by using light emitted from a light emitting device including an emission layer disposed between two electrodes
Implementation Method 2
due to a parasitic capacitance formed in an overlap region (or an intersection region) between the horizontal signal line and the vertical signal line
Data Source
AI summary
A light emitting display apparatus includes a plurality of pixels each including a plurality of subpixels, a plurality of data lines respectively connected with the plurality of subpixels, and a plurality of reference lines in each of the plurality of pixels. Each of the plurality of subpixels includes a pixel circuit connected with a corresponding data line and a corresponding reference line and a light emitting device layer connected with the pixel circuit. A first subpixel group among the plurality of subpixels in each of the plurality of pixels is connected with a corresponding reference line, and a second subpixel group except the first subpixel group among the plurality of subpixels in each of the plurality of pixels is connected with a reference line connected with an adjacent different pixel.