Display Refresh Rate Switching via Dual Register Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display refresh rate adjustment methods require disconnecting graphics heads and involve noticeable mode switches, leading to artifacts such as data loss or visual interruptions during the transition between refresh rates.
Innovation Solution
A system and method that utilize two registers to store refresh parameters for different rates and logic to select between them, allowing for seamless transitions during active periods when pixels are being written to the display, thereby reducing artifacts by updating display timing registers without interrupting the rendering process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If display refresh rate is adjusted by mode switch, then refresh rate can be changed, but artifacts such as data loss or visual interruptions occur
Solution Approach 1:
The patent applies preliminary action by pre-loading refresh parameters into two separate registers (first and second registers) before a mode switch is needed. When a refresh rate change is requested, the system can immediately switch between pre-configured parameters without interruption, eliminating visual artifacts. The logic circuit is designed in advance to select between registers based on timing signals, ensuring seamless transitions.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of dual registers and timing logic that mediates the transition between refresh rates. Instead of directly switching modes which causes artifacts, the system uses these intermediate storage elements to buffer parameter changes, allowing smooth transitions during vertical blanking periods when the display is not actively rendering pixels.
2Adaptability or versatility
If mode switch is performed to adjust refresh rate, then refresh rate can be changed, but graphics head must be disconnected
Solution Approach 1:
The system performs preliminary configuration by storing multiple refresh parameters in advance in separate registers. This allows the graphics head to remain connected while parameters are switched, as the switching logic is pre-built into the display controller. The operation becomes as simple as changing which register is active, rather than requiring physical disconnection and reconfiguration.
Solution Approach 2:
The patent replaces the mechanical approach of physically disconnecting and reconnecting the graphics head with an electronic parameter switching mechanism. The dual-register system with timing-based selection logic provides a purely electronic method for changing refresh rates, eliminating the need for mechanical intervention and maintaining continuous graphical output.
3Productivity
If refresh rate change is made during active period, then continuous rendering is maintained, but artifacts may occur
Solution Approach 1:
The patent applies local quality by making the parameter switching operation local to the timing control logic rather than affecting the entire rendering pipeline. By confining the register selection change to occur during vertical blanking periods (when no pixels are being written), the system maintains high-quality continuous rendering during active periods while performing parameter changes in localized inactive intervals.
Solution Approach 2:
The system uses periodic action by timing the refresh parameter switches to occur during vertical blanking periods, which are regular, periodic intervals in the display refresh cycle. This periodic scheduling ensures that parameter changes happen at predictable moments when the display is naturally transitioning between frames, preventing artifacts while maintaining continuous rendering capability.
Data Source
AI summary
A system and method are provided for changing a display refresh rate. A first register is provided for storing at least one first refresh parameter in association with a first refresh rate. Additionally, a second register is provided for storing at least one second refresh parameter in association with a second refresh rate. Furthermore, logic is in communication with the first register and the second register. Such logic is adopted for selecting the first refresh parameter or the second refresh parameter, for the purpose of reducing artifacts resulting from a change from the first refresh rate and the second refresh rate.