Display Render Unit Video Latency Reduction via Dynamic Pixel Clock
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Solution Overview
Problem
Video recording systems, such as e-mirrors in the automobile industry, experience video latency due to delays in image processing and transmission, affecting efficiency.
Innovation Solution
A receiving device and video recording system that utilize a processor, memory, and communication interface to determine and reduce video latency by implementing accelerating schemes at the display render unit or video capture unit, based on target and current line counts, to optimize pixel clock frequencies and synchronization signal durations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If video transmission is performed using standard pixel clock frequency and processing speed, then system stability and processing accuracy are maintained, but video latency increases and system efficiency decreases
Solution Approach 1:
The patent applies dynamics by making the pixel clock frequency adjustable rather than fixed. The system dynamically changes the pixel clock frequency from a first frequency to a second frequency based on whether acceleration is needed, allowing the display render unit to adapt its processing speed to reduce video latency when necessary while maintaining stability during normal operation
Solution Approach 2:
The patent implements parameter changes by modifying the pixel clock frequency parameter. The processor determines whether to accelerate video transmission by changing the pixel clock frequency, which directly affects the processing speed of the display render unit. This parameter change enables the system to reduce video latency by accelerating frame rendering when target reduced latency is determined
2Loss of time
If video transmission is accelerated by changing pixel clock frequency, then video latency is reduced, but energy consumption increases
Solution Approach 1:
The patent applies periodic action by implementing intermittent acceleration rather than continuous acceleration. The processor periodically determines whether acceleration is needed based on video latency requirements, and only accelerates the pixel clock frequency when target reduced latency is determined. This periodic approach reduces energy consumption compared to continuous high-speed operation while still achieving latency reduction when necessary
Solution Approach 2:
The system dynamically adjusts the pixel clock frequency based on real-time latency requirements. Instead of maintaining high frequency continuously, the system switches between first frequency (normal operation) and second frequency (accelerated operation) only when needed, optimizing the balance between video latency reduction and energy consumption
Data Source
AI summary
A receiving device for reducing video latency includes a display render unit, a communication interface, a memory, and a processor. The display render unit performs a video transmission to output a video to a display apparatus. The video generated by a video capture unit of the sending device is transmitted through the communication interface to the receiving device. The memory stores at least one computer readable instruction. The processor accesses and executes the at least one computer readable instruction to: determine whether a video latency is necessary to be reduced; determine a target reduced latency based on a target line count and a current line count; and determine a first period based on the target reduced latency and an accelerating scheme at the display render unit. The display render unit performs the video transmission to the display apparatus based on the accelerating scheme for the first period.