Multi-Layer Display Routing for Narrow-Bezel Image Quality

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Solution Overview

Problem

Current display devices have a significant non-display region, known as the bezel, which reduces the effective display area and affects image quality due to the placement of power lines and data signals, making it challenging to minimize the bezel while maintaining image quality.

Innovation Solution

The display device incorporates a substrate with multiple display regions and a non-display region where power lines and data signals are efficiently routed using fan-out lines and power lines with additional layers and insulating layers to minimize the bezel area, allowing for a more compact design without compromising image quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If power lines and data signals are routed through the non-display region (bezel), then the display area can be maximized, but the bezel area increases and image quality deteriorates

Engineering Contradiction:
Improvedisplay areaVSAvoidbezel area
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The patent applies dimensionality change by routing power lines and data signals through multiple layers (vertical dimension) rather than spreading them horizontally across the bezel. The fan-out lines extend in first and second directions with multiple layers stacked vertically, allowing signals to reach pixels without expanding the horizontal bezel area. This layered approach transforms a 2D routing problem into a 3D solution, minimizing the visible bezel while maintaining signal delivery capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If power lines are placed in the non-display region, then power delivery is simplified, but the bezel area increases and image quality is affected

Engineering Contradiction:
Improvepower deliveryVSAvoidbezel area
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent implements nesting by placing multiple power lines and signal lines within a compact fan-out structure in the non-display region. The additional power line is positioned to overlap with existing power lines in the plan view, creating a nested arrangement where multiple conductors share the same spatial footprint. This nested configuration delivers multiple power signals without proportionally increasing the bezel area, as the lines are stacked vertically rather than spread horizontally.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Object-generated harmful factors

If fan-out lines are used to route data signals, then the bezel area is minimized, but the device complexity increases due to additional layers and routing structures

Engineering Contradiction:
Improvebezel areaVSAvoidrouting structure
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the fan-out line structure into distinct segments: first fan-out lines extending in a first direction, second fan-out lines extending in a second direction, and additional fan-out lines for specific pixel columns. This segmented approach allows each segment to be optimized independently for its specific routing function, making the overall complex structure more manageable and manufacturable despite the multiple layers and directions involved.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240284738A1Display device
Publication Date: 2024.08.22 SAMSUNG DISPLAY CO LTD
  • US20240284738A1 patent drawing
  • US20240284738A1 patent drawing
  • US20240284738A1 patent drawing

AI summary

A display device includes a substrate including a first display region, a second display region having an area smaller than that of the first display region, a third display region having an area smaller than that of the first display region, and a non-display region, a plurality of pixels provided in the first to third display regions, a power line which is connected to each of the plurality of pixels and applies a first power voltage to the plurality of pixels, and a fan-out line provided in the non-display region, the fan-out line applying a data signal to the plurality of pixels, where the power line includes an additional power line, a first power line, and disposed on the additional power line, and a second power line disposed on the first power line.