Display Row Drive Circuit for High-Refresh Switching Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Switching tubes in liquid crystal panels, particularly in high refresh rate displays with freesync functions, experience prolonged exposure to high voltage or current, leading to drift in their volt-ampere characteristics and abnormal lighting.
Innovation Solution
A drive circuit design with cascaded array substrate row driving units, incorporating pull-up and pull-down modules, inverting modules, and a clock signal with multiple levels to manage the potential of nodes during image blanking periods, reducing the time switching transistors are exposed to high voltage or current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the clock signal blanking time is extended to support freesync function, then the display can adjust refresh rate to be consistent with game frame rate, but the switching tubes are subjected to high voltage or current for a longer time causing volt-ampere characteristics to drift
Solution Approach 1:
The patent applies preliminary action by resetting the clock signal to a first level (low level) before the switching tube needs to be turned off. This preliminary reset action reduces the blanking time that the switching tube is exposed to high voltage or current, thereby preventing volt-ampere characteristic drift while still allowing the freesync function to operate.
2Reliability
If the clock signal is reset to first level before switching tube turn-off, then the exposure time to high voltage or current is reduced, but the control logic becomes more complex
Solution Approach 1:
The patent applies dynamics by making the clock signal dynamic rather than static. The clock signal transitions through multiple levels (first level, second level, third level) at different times during the scanning process. This dynamic approach allows the system to reduce exposure time to high voltage/current while maintaining clear control logic through defined signal transitions.
3Reliability
If the clock signal has multiple levels with specific timing, then the potential of nodes can be controlled to reduce switching tube exposure time, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by varying the clock signal through different voltage levels (first level, second level, third level) at specific timing intervals. This parameter variation allows precise control over when nodes are pulled up or down, enabling reduced exposure time of switching tubes to high voltage/current while providing manufacturing flexibility through standard signal generation capabilities.
Data Source
AI summary
A drive circuit and a control method thereof, and a storage medium are disclosed in the present disclosure. In the present disclosure, a clock signal is at a second level during an image blanking period, and a potential of a third node is reset to a low level, so that the switching transistor is subjected to a high point voltage or a high current for a shortened time, and the potential of the third node is pulled down early, thereby preventing a third switching transistor, a fourth switching transistor, a sixteenth switching transistor, and a seventeenth switching transistor from being under the action of the high voltage or the high current for a long time.