Display Device Sampling Transistor Wiring Segmentation
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Solution Overview
Problem
Existing display devices, particularly liquid crystal and organic EL display devices, face challenges in achieving larger screen sizes and higher definitions due to signal delays and increased manufacturing costs associated with complex wiring structures, which lead to difficulties in proper video signal sampling timings.
Innovation Solution
The implementation of a high-fusion-point metal wiring layer and an overlying wiring layer with multiple contact holes for each wiring connection section, allowing for reduced signal delays and improved sampling timings, while maintaining low manufacturing costs by minimizing the number of additional layers and contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a complex wiring structure with multiple layers and contacts is used to reduce signal delays, then sampling timing precision is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The pixel array is divided into multiple blocks, with each block containing a subset of pixels that share common wiring resources. This segmentation allows for reduced wiring complexity within each block while maintaining overall coverage, thereby reducing signal delays without requiring a fully complex wiring structure across the entire display
Solution Approach 2:
The patent introduces a block-based organizational dimension beyond the traditional row-column pixel addressing. By grouping pixels into blocks and implementing wiring at the block level, the patent creates a hierarchical wiring structure that reduces the number of wiring layers and contacts needed compared to a fully distributed wiring approach
2Area of stationary object
If the screen size is increased while maintaining definition, then the display area is improved, but signal delays increase making proper sampling timing difficult
Solution Approach 1:
The large display screen is segmented into multiple blocks of pixels. Each block can be addressed and driven independently with shorter wiring paths, reducing the maximum signal transmission distance and delay across the entire display area
Solution Approach 2:
The patent pre-organizes pixels into blocks with assigned block addresses, allowing the display controller to efficiently manage signal routing. This preliminary organizational structure enables optimized signal paths that reduce transmission delays across large screen areas
3Manufacturing precision
If the definition is increased while maintaining screen size, then the image quality is improved, but the wiring structure becomes more complex increasing manufacturing cost
Solution Approach 1:
High-definition pixel arrays are divided into blocks that share common wiring resources. This segmentation reduces the total number of independent wiring paths needed, simplifying the wiring structure and reducing manufacturing complexity while maintaining high definition through increased pixel density within each block
Solution Approach 2:
Wiring structures are designed to serve multiple pixel blocks simultaneously. Common wirings can address multiple blocks, reducing the total wiring count needed for high-definition displays and thereby reducing manufacturing complexity and cost
Data Source
AI summary
A display device including a pixel array having a plurality of pixels arranged in a matrix form, each of the pixels including a sampling transistor configured to sample a data potential from a video signal line which is insulated from and intersects a control line in response to the change in potential of the control line, and a light-emitting element configured to emit light at the brightness commensurate with the magnitude of the post-sampling data potential.