Display Scaler Position Error Reduction via Locking Mechanisms
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display device scalers face challenges in accurately upscaling image resolution due to unacceptable ratio factors for digital circuits, leading to position errors and deteriorated imaging quality, especially when converting lower resolutions to higher resolutions like 640×480 to 1440×1050, where vertical and horizontal exact ratio factors like 16/35 and 4/9 are not acceptable, resulting in errors and delayed processing.
Innovation Solution
Implementing a global locking mechanism and a local locking mechanism to determine the actual position of interpolated pixels, reducing position errors by adjusting the position error accumulation and recalculating pixel values, thereby enhancing the imaging quality of the output image signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If linear interpolation is performed using exact ratio factors (e.g., 16/35, 4/9) for upscaling, then manufacturing precision of pixel positioning is improved, but device complexity increases and processing speed decreases due to digital circuit limitations
Solution Approach 1:
The patent changes the ratio factor parameter from exact fractional values (16/35, 4/9) to approximate values with denominators that are powers of 2 (e.g., 32/1024, 16/512). This parameter transformation enables the use of simple bit-shifting operations instead of complex division, significantly improving processing speed while maintaining acceptable pixel positioning accuracy for display purposes
2Manufacturing precision
If linear interpolation is performed using exact ratio factors, then manufacturing precision is improved, but device complexity increases due to unacceptable ratio factors for digital circuits
Solution Approach 1:
The patent transforms the ratio factor parameters into forms suitable for digital circuit implementation by using denominators that are powers of 2. This allows the use of simple bit-shifting and addition operations instead of complex division circuits, significantly reducing device complexity while maintaining functional equivalence for display resolution scaling
Solution Approach 2:
The patent accepts approximate rather than exact ratio factors, trading mathematical precision for computational simplicity. The approximation error is negligible for display purposes, enabling the use of simple, fast, and resource-efficient algorithms instead of complex precise calculations
3Manufacturing precision
If global locking mechanism is used to reduce position errors, then imaging quality is improved, but processing time increases due to recalculation requirements
Solution Approach 1:
The patent applies the locking mechanism at predetermined intervals (every A lines or B pixels) rather than continuously. This preliminary action at key intervals prevents error accumulation without requiring constant recalculation, significantly reducing processing time while maintaining position accuracy within acceptable bounds between locking points
Data Source
AI summary
A scaling-up control method and a scaling-up control apparatus are used in a display device. The display device includes a scaler for converting an original image signal into an output image signal by performing a linear interpolation. Moreover, by utilizing a global locking mechanism and a local locking mechanism to perform the linear interpolation to determine the actual position of the interpolated pixel, the position error of the pixel position is largely reduced. Since the difference between the calculated pixel value and the ideal pixel value is reduced, the imaging quality of the output image signal is enhanced.