Display Scan Circuit With Differential Clock-Line Widths
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Solution Overview
Problem
Existing display technologies face challenges in efficiently controlling image display in pixel rows due to limitations in gate driving circuits, particularly in achieving uniform luminance and phase synchronization of control signals across adjacent rows of subpixels.
Innovation Solution
The implementation of a display apparatus with alternately arranged scan circuits, including first and second scan units providing out-of-phase control signals to adjacent rows of subpixels, and third scan units providing in-phase signals, along with differential clock and signal line widths and loadings, to enhance control signal synchronization and luminance uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock signal line is used to provide clock signals to scan units, then the circuit structure is simple, but signal interference increases and luminance uniformity deteriorates
Solution Approach 1:
The patent divides the single clock signal line into multiple separate clock signal lines (first clock signal line and second clock signal line) to provide clock signals to different scan units. This segmentation reduces signal interference between adjacent rows and improves luminance uniformity across the display panel.
Solution Approach 2:
The patent applies different line widths to different clock signal lines based on their specific requirements. The first clock signal line has a first line width while the second clock signal line has a second line width, allowing each signal line to be optimized for its local signal transmission needs, thereby reducing interference and improving overall reliability.
2Ease of manufacture
If uniform line widths are used for all clock signal lines, then the manufacturing process is simple, but signal transmission quality and synchronization deteriorate
Solution Approach 1:
The patent specifies that the first clock signal line has a first line width and the second clock signal line has a second line width, with the second line width being greater than the first line width by 0.1% to 20%. This local differentiation allows each signal line to be optimized for its specific transmission requirements, improving signal quality and synchronization while maintaining a relatively simple manufacturing process.
3Device complexity
If adjacent rows use in-phase control signals, then the circuit design is simple, but luminance uniformity deteriorates due to signal interference
Solution Approach 1:
The patent inverts the conventional approach by using out-of-phase control signals for adjacent rows instead of in-phase signals. The first scan unit and second scan unit provide control signals that are out of phase, which reduces signal interference between adjacent rows and improves luminance uniformity across the display.
4Ease of manufacture
If clock signal line width is not optimized, then the manufacturing process is simple, but signal interference increases and display performance deteriorates
Solution Approach 1:
The patent optimizes the line width parameter of clock signal lines to reduce signal interference. Specifically, the second clock signal line has a greater line width than the first clock signal line by 0.1% to 20%, which allows for better signal transmission quality and reduced interference while maintaining a relatively simple manufacturing process.
Data Source
AI summary
A display apparatus includes a first scan circuit. The first scan circuit includes a plurality of first scan units and a plurality of second scan units. The display apparatus further includes a first clock signal line configured to provide a first clock signal to a respective first scan unit of the plurality of first scan units or a respective second scan unit of the plurality of second scan units; and a second clock signal line configured to provide a second clock signal to the respective first scan unit or the respective second scan unit. The first clock signal line has a first line width. The second clock signal line has a second line width. The second line width of the second clock signal line is greater than the first line width of the first clock signal line by 0.1% to 20%.