Display Scan-Stage Circuit Layout for Peripheral Dead Space
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices face inefficiencies in utilizing dead spaces and lack uniformity in pixel and driver arrangements, leading to suboptimal performance.
Innovation Solution
The display device incorporates varying gaps and dummy circuits between scan and emission stage circuits in peripheral areas, optimizing the use of dead spaces and enhancing uniformity by adjusting the positions and numbers of these circuits based on specific pixel areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If drivers are embedded in the display device, then integration is improved, but dead space is formed reducing efficiency
Solution Approach 1:
The patent converts the harmful dead space formed by embedded drivers into a beneficial region by placing scan stage circuits and emission stage circuits within it. This transforms previously wasted space into functional circuit housing, achieving dual-purpose utilization of the same area.
Solution Approach 2:
The patent utilizes the peripheral area surrounding the pixel array in a different dimensional arrangement, placing scan stage circuits and emission stage circuits in the gap between the pixel array and the display device boundary, thereby efficiently using space that would otherwise be unused.
2Ease of manufacture
If uniform gaps are used between scan stage circuits, then manufacturing is simplified, but dead space utilization is inefficient
Solution Approach 1:
The patent applies different gap sizes at different locations between scan stage circuits. Specifically, a first gap is used between adjacent scan stage circuits in one direction, while a second gap (different from the first gap) is used between scan stage circuits and the display device boundary or in other directions, optimizing space utilization for each specific location.
Solution Approach 2:
The patent introduces asymmetric gap arrangements where the distance between scan stage circuits varies depending on their position. This asymmetric design allows better fitting of circuits into the peripheral dead space while maintaining electrical performance requirements.
3Manufacturing precision
If pixel areas are made smaller to increase resolution, then display quality is improved, but peripheral area for circuits is reduced
Solution Approach 1:
The patent places scan stage circuits and emission stage circuits in the peripheral dimension, utilizing the boundary area between the pixel array and display device edge. This dimensional reorganization allows circuit placement without encroaching on the pixel array area, maintaining high resolution while providing sufficient circuit space.
Data Source
AI summary
A display device includes first pixels configured to be positioned in a first pixel area and configured to be connected to first scan lines; first scan stage circuits configured to be positioned in a first peripheral area that is positioned outside the first pixel area and configured to supply first scan signals to the first scan lines; second pixels configured to be positioned in a second pixel area and configured to be connected to second scan lines; and second scan stage circuits configured to be positioned in a second peripheral area that is positioned outside the second pixel area and configured to supply second scan signals to the second scan lines. A gap between adjacent second scan stage circuits is larger than a gap between adjacent first scan stage circuits.