Display Scan Driver Layout With Dummy Holes for Signal Accuracy

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Solution Overview

Problem

Existing display apparatuses face challenges in accurately generating scan signals, which affects the quality of images displayed, particularly due to the arrangement of transistors and electrodes in the display area and peripheral areas.

Innovation Solution

The display apparatus incorporates a substrate with a display area and peripheral area, featuring transistors with specific semiconductor layers and gate electrodes, along with insulating layers and dummy holes to improve signal accuracy and quality, including a scan driver with stages and output terminals connected to the first transistor, which includes an oxide semiconductor layer and a second transistor with a silicon semiconductor layer, ensuring precise signal generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If transistors and electrodes are arranged in the display area and peripheral area, then the display apparatus can control brightness and transfer scan signals, but the scan signal generation accuracy deteriorates

Engineering Contradiction:
Improvescan signal generation accuracyVSAvoidarrangement of transistors and electrodes
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The scan driver is divided into multiple stages, with each stage containing specific transistors (first transistor with oxide semiconductor, second transistor with silicon semiconductor) and electrodes arranged in a segmented manner. This segmentation allows independent optimization of each stage's signal generation accuracy while managing overall device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different semiconductor materials are used in different locations: oxide semiconductor in the first transistor for low-temperature processing and silicon semiconductor in the second transistor for high mobility. Dummy holes are strategically positioned at specific locations to improve interface quality. This local quality approach optimizes scan signal generation accuracy at critical positions without requiring complete redesign of the entire structure.

Inventive Principle:
Principle #3Local quality

2Measurement precision

If dummy holes are added to improve scan signal accuracy, then signal generation quality improves, but device structure complexity increases

Engineering Contradiction:
Improvescan signal accuracyVSAvoidstructure with dummy holes
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Dummy holes are created in the insulating layer before final electrode formation. This preliminary action prepares the structure for improved signal accuracy by removing defects and improving interface quality in advance, allowing subsequent electrodes to be formed with better characteristics without adding excessive complexity to the final structure.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy holes act as intermediary structures that mediate between the insulating layer and the electrodes. They improve the interface quality and signal transmission characteristics without requiring direct modification of the electrode design itself, thus improving scan signal accuracy while maintaining relatively simple electrode structures.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240321909A1Display apparatus
Publication Date: 2024.09.26 SAMSUNG DISPLAY CO LTD
  • US20240321909A1 patent drawing
  • US20240321909A1 patent drawing
  • US20240321909A1 patent drawing

AI summary

A display apparatus includes a substrate having a display area and a peripheral area outside the display area, a transistor in the display area and a light-emitting element electrically connected to the transistor, and a scan driver in the peripheral area, wherein the scan driver includes a first transistor disposed on the substrate and including a first semiconductor layer comprising an oxide semiconductor and a first gate electrode overlapping the first semiconductor layer, a second transistor disposed on the substrate and including a second semiconductor layer comprising a silicon semiconductor and a second gate electrode overlapping the second semiconductor layer, and insulating layers disposed on the substrate and defining dummy holes not overlapping the first semiconductor layer and the second semiconductor layer, wherein the dummy holes are spaced apart from the first semiconductor layer and the second semiconductor layer and overlap dummy semiconductor layers adjacent to the first semiconductor layer.