Display Scan Driver Stage With Local Clock Output Circuits
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Solution Overview
Problem
Existing electronic devices have a significant non-display area that consumes power and reduces the overall efficiency and aesthetic appeal.
Innovation Solution
The electronic device incorporates a stage with a node control circuit and multiple output circuits, including transistors and capacitors, to manage clock signals and voltages, reducing power consumption and minimizing the non-display area by optimizing scan line operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional display panel structure is used, then the display area is sufficient, but the non-display area (bezel area) becomes large and consumes power
Solution Approach 1:
The patent extracts the clock signal generation function from a centralized source and distributes it to multiple output circuits throughout the display panel. By taking out the clock signal generation capability and placing it locally at each output circuit, the patent eliminates the need for extensive clock signal distribution wiring across the entire panel, thereby reducing the non-display area while maintaining proper clock signal delivery to all pixels. This extraction principle directly addresses the contradiction by removing unnecessary infrastructure that contributes to both bezel size and power consumption.
Solution Approach 2:
The patent segments the clock signal distribution system into multiple independent output circuits, each capable of generating and distributing clock signals locally to its associated scan lines. Instead of using a single centralized clock source that requires long distribution paths, the system divides the clock signal generation into discrete segments at each output circuit. This segmentation reduces the overall wiring requirements and non-display area while lowering power consumption through localized signal generation.
2Productivity
If the non-display area is reduced, then the display efficiency improves, but the circuit complexity increases
Solution Approach 1:
The patent merges multiple functions into each output circuit: clock signal generation, signal distribution to multiple scan lines, and voltage level management. By combining these functions into integrated output circuits rather than using separate dedicated circuits for each function, the patent reduces overall circuit complexity while achieving reduced non-display area. The merging of functions allows the system to maintain high display efficiency without proportionally increasing circuit complexity.
Solution Approach 2:
Each output circuit in the patent is designed as a universal module that can handle multiple scan lines and generate clock signals independently. This multi-functionality means that each output circuit serves multiple purposes: generating clock signals, distributing them to multiple scan lines, and managing voltage levels. The universal design reduces the total number of circuits needed, thereby reducing non-display area while keeping circuit complexity manageable through standardized reusable modules.
Data Source
AI summary
An electronic device includes a stage. The stage includes a node control circuit; a first transistor connected between a first power line and a first output node; a first capacitor connected between a gate electrode of the first transistor and the first output node; a second transistor connected between a first clock line and a second output node; a second capacitor connected between a gate electrode of the second transistor and the second output node; a third transistor connected between a second clock line and a third output node; a third capacitor connected between a gate electrode of the third transistor and the third output node; and a fourth transistor connected between a first node and the gate electrode of the first transistor, and maintained in a turn-on state in response to a first voltage.