Display Scan Driver Timing for Frame-Adaptive Power Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Display devices face high power consumption due to the frequency of clock signals, particularly in scan drivers, which is not optimally managed based on the type of frame being displayed.

Innovation Solution

The display device adjusts the frequency of clock signals and emission signals based on the frame type, using different periods for scan and emission drivers to optimize power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the frequency of clock signals is increased to improve display performance, then the display quality is improved, but power consumption increases

Engineering Contradiction:
Improvedisplay performanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the clock signal frequency adjustable rather than fixed. The driving circuit changes the frequency of clock signals supplied to scan drivers and emission drivers based on the frame type (first frame period vs. second frame period), allowing the system to adapt its operating speed to match display requirements and minimize power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements parameter changes by modifying the frequency parameter of clock signals according to different frame types. Specifically, the frequency is set to a first frequency during first frame periods and a second frequency during second frame periods, where the second frequency differs from the first. This parameter adjustment enables optimization of power consumption while maintaining display performance.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If a single clock signal frequency is used for all frame types, then device complexity is reduced, but power consumption optimization is limited

Engineering Contradiction:
Improveclock signal managementVSAvoidpower consumption efficiency
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent applies universality by designing a driving circuit that can handle multiple frame types (first frame period and second frame period) using a unified control architecture. The same driving circuit generates different clock signal frequencies based on the frame type, eliminating the need for separate dedicated circuits for each frame type while achieving power consumption optimization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12394355B2Display device and driving method thereof
Publication Date: 2025.08.19 SAMSUNG DISPLAY CO LTD
  • US12394355B2 patent drawing
  • US12394355B2 patent drawing
  • US12394355B2 patent drawing

AI summary

A display device includes: a first pixel connected to a first data line and a first scan line; a second pixel connected to the first data line and a second scan line; a first scan driver connected to a first scan start line and the first scan line; and a second scan driver connected to a second scan start line and the second scan line. In a first frame period, the second scan start line is to be suppled with a second scan start signal having a turn-on level, after a first period elapses after a first scan start signal having a turn-on level is supplied to the first scan start line. In a second frame period, a difference between a time at which the first scan start signal having the turn-on level is supplied and a time at which the second scan start signal having the turn-on level is supplied corresponds to a second period. The second period is shorter than the first period.