Display Panel Scan Pull-Down Circuits for High-Resolution Stability

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Solution Overview

Problem

The increasing resolution of display panels leads to over-loading in display areas, causing display abnormalities.

Innovation Solution

A display panel design incorporating N scan lines and J sets of forward and reverse scan pull-down circuits, with output terminals connected in a one-to-one correspondence, to rapidly pull down scan signal falling edges, reducing delays and improving display quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the resolution of the display panel is increased to provide ultra-high resolution, then the display quality is improved, but the loading in the display area increases causing over-loading and display abnormalities

Engineering Contradiction:
Improvedisplay resolutionVSAvoiddisplay stability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The gate driving function is segmented into multiple independent gate driving units distributed across different regions of the display panel. Each gate driving unit independently drives a portion of the scan lines, dividing the overall driving task to reduce the loading on any single unit and improve display stability at ultra-high resolution

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a two-dimensional array of gate driving units (J rows and K columns) instead of a single linear gate driving circuit. This spatial distribution across multiple dimensions reduces the signal transmission distance and loading on individual circuits, enabling stable operation at ultra-high resolutions

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If more scan lines are added to increase resolution, then the display detail is improved, but the scan signal delay increases causing display abnormalities

Engineering Contradiction:
Improvedisplay resolutionVSAvoidscan signal delay
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The scan lines are divided into multiple groups, with each gate driving unit responsible for driving a specific subset of scan lines. This segmentation reduces the number of scan lines each unit must drive sequentially, thereby reducing scan signal delay while maintaining ultra-high resolution capability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple gate driving units are positioned at different locations across the display panel to preliminarily prepare scan signals at various regions simultaneously. This parallel preparation of scan signals reduces the overall scanning time and delay across the entire high-resolution display

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250384844A1Display panel and display device
Publication Date: 2025.12.18 WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
  • US20250384844A1 patent drawing
  • US20250384844A1 patent drawing
  • US20250384844A1 patent drawing

AI summary

The present application provides a display panel and a display device, the display panel includes: N scan lines, the N is an integer greater than or equal to 1; and J sets of forward and reverse scan pull-down circuits, each set of the forward and reverse scan pull-down circuits includes N forward and reverse scan pull-down modules, at least a part of each of the forward and reverse scan pull-down modules is disposed in the display subarea, and the J is an integer greater than or equal to 1. In each set of the forward and reverse scan pull-down circuits, output terminals of the N forward and reverse scan pull-down modules are connected to the N scan lines in a one-to-one correspondence.