Display Panel Scan Timing Layout for Vertical Stripe Reduction

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Solution Overview

Problem

Display panels exhibit vertical stripes due to differences in data signal timing across pixels in the same row, caused by signal terminals in data driving circuits, leading to inconsistent luminous brightness.

Innovation Solution

Implementing a display panel design where at least some pixels in the same row are connected to the same scan line and column data line, with controlled enable levels of scan signals to synchronize data signal writing, ensuring consistent pre-writing and data writing stages across pixels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If data signals are provided to each pixel through separate data lines with individual timing, then each pixel can be addressed independently, but the signal timing differences cause inconsistent luminous brightness and vertical stripes

Engineering Contradiction:
Improvedisplay uniformityVSAvoidsignal terminal configuration
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the data signal transmission for multiple pixels in the same row by using a shared data line and synchronized write control. Instead of providing data signals to each pixel through separate timing paths, the invention combines the writing process so that all pixels in a row receive their data signals during the same time period, eliminating the timing differences that cause vertical stripes while maintaining independent pixel addressing capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements a pre-writing stage before the formal data writing stage. During this preliminary action, data signals are prepared and made available to the data lines before the actual pixel writing begins. This ensures that when the write operation starts, all pixels are ready to receive their data signals simultaneously, preventing timing mismatches and ensuring uniform display across all pixels in the row

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the pre-writing stage and data writing stage are separated, then data signals can be prepared in advance, but the timing coordination becomes complex

Engineering Contradiction:
Improvedata signal accuracyVSAvoidwriting cycle duration
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent makes the pre-writing stage and data writing stage occur in continuous overlap rather than as separate sequential operations. The pre-writing preparation continues throughout the data writing process, ensuring that data signals are always ready when needed. This continuous action approach maintains data signal accuracy while minimizing the total writing cycle time, as the preparation and execution phases run concurrently rather than sequentially

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20260065857A1Display panel and display device
Publication Date: 2026.03.05 WUHAN TIANMA MICRO ELECTRONICS CO LTD
  • US20260065857A1 patent drawing
  • US20260065857A1 patent drawing
  • US20260065857A1 patent drawing

AI summary

A display panel includes pixels arranged in an array, data lines, and first scan lines. At least a portion of pixels in a same row is electrically connected to a same first scan line. At least a portion of pixels in a same column is electrically connected to a same data line. The pixels at least include first pixels whose luminous color is a first color. A driving cycle of a pixel includes a pre-writing stage, where a data signal of the pixel is written to a data line electrically connected to the pixel; and a data writing stage, where a data signal on the data line electrically connected to the pixel is written to the pixel. At least in the data writing stage of the pixel, the first scan line electrically connected to the pixel transmits an enable level of the first scan signal.