Display Device With Segmented Semiconductor Layers
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Solution Overview
Problem
Current display manufacturing processes are complicated due to the incompatibility of processes for producing polycrystalline silicon thin film transistors (TFTs) and metal oxide TFTs, making it challenging to create a substrate with both types of transistors.
Innovation Solution
A substrate assembly comprising a substrate with two types of transistors: a first transistor with a silicon semiconductor layer and a second transistor with an oxide semiconductor layer, where the semiconductor layers are electrically insulated from each other, allowing for simultaneous integration on the same substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both polycrystalline silicon TFT and metal oxide TFT are integrated on the same substrate, then display quality and efficiency are improved, but manufacturing process complexity increases
Solution Approach 1:
The substrate is divided into different regions with different semiconductor layers: a first region with polycrystalline silicon semiconductor layer for high-speed switching TFTs, and a second region with oxide semiconductor layer for low-leakage TFTs. This segmentation allows each transistor type to be optimized independently while coexisting on the same substrate, improving display quality without requiring complete process redesign.
Solution Approach 2:
Different semiconductor materials are used in different local regions of the substrate according to specific functional requirements. The polycrystalline silicon is used where high carrier mobility is needed, while oxide semiconductor is used where low leakage current is critical. This local quality approach resolves the contradiction by allowing process complexity to be managed locally rather than globally.
2Ease of manufacture
If polycrystalline silicon TFT and metal oxide TFT are manufactured using compatible processes, then manufacturing complexity is reduced, but process compatibility is limited
Solution Approach 1:
The manufacturing process is designed to be universal, using the same substrate, similar deposition techniques, and compatible processing steps for both polycrystalline silicon and oxide semiconductor layers. The process can accommodate multiple transistor types on the same substrate by selectively forming different semiconductor layers in different regions, achieving both ease of manufacture and adaptability.
Solution Approach 2:
A buffer layer is introduced as an intermediary between the substrate and the semiconductor layers. This buffer layer facilitates the formation of both polycrystalline silicon and oxide semiconductor layers using compatible processes, acting as a mediator that enables process compatibility while allowing versatility in transistor type integration.
3Reliability
If different semiconductor layers are used for different transistors, then transistor performance is optimized, but electrical insulation between layers becomes challenging
Solution Approach 1:
An insulating layer is introduced as an intermediary between the first semiconductor layer (polycrystalline silicon) and the second semiconductor layer (oxide semiconductor). This insulating layer effectively prevents electrical interference between the different semiconductor layers while allowing each layer to maintain its optimized transistor performance, resolving the contradiction between performance optimization and insulation complexity.
Data Source
AI summary
A substrate assembly includes: a substrate; a first transistor disposed on the substrate, wherein the first transistor includes a first semiconductor layer; and a second transistor disposed on the substrate, wherein the second transistor includes a second semiconductor layer and a drain electrode electrically connected to the second semiconductor layer, and a material of the first semiconductor layer is different from a material of the second semiconductor layer, wherein the first semiconductor layer of the first transistor is electrically insulated from the drain electrode of the second transistor.