Flat Panel Display Serializer Clocking to Reduce EMI and Timing Skew
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Solution Overview
Problem
High-resolution flat plate displays face electromagnetic interference (EMI) issues due to increased data transmission frequency, leading to unstable device driving and errors in data restoration caused by independent clock timing changes with power, voltage, and temperature variations.
Innovation Solution
A data transmitting device that includes a clock generator to produce multiple phase-shifted clocks and a serializer to convert parallel image data and dot-clock into high-speed serial data and clock, ensuring synchronized timing through phase-locked loops and ring counters, which are then converted into differential signals to minimize timing skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If data transmission frequency is increased to achieve high-resolution display, then display quality is improved, but electromagnetic interference increases causing unstable device driving
Solution Approach 1:
The patent replaces traditional parallel data transmission with serial data transmission using LVDS (Low Voltage Differential Signal) technology. This substitution converts multiple parallel data lines into a single serial data stream transmitted at high frequency, reducing the number of transmission lines and minimizing electromagnetic interference while maintaining high-resolution display quality.
Solution Approach 2:
The patent changes the transmission mode from parallel to serial, and adjusts voltage levels to low voltage differential signals. By transforming the data transmission parameters (serializing data and using differential signaling), the system achieves high data rates necessary for high-resolution displays while reducing electromagnetic interference through controlled impedance matching and differential signal characteristics.
2Ease of operation
If separate logic buffers are used to adjust clock timing, then clock timing can be adjusted independently, but timing skew between data and clock increases under power and temperature changes
Solution Approach 1:
The patent merges the data path and clock path by passing both through the same serializer circuit. This integration ensures that data and clock signals experience identical delays and processing conditions, automatically maintaining their timing relationship. The serializer processes both signals through identical logic stages, eliminating the timing skew problems that occur with separate buffer adjustments under varying power and temperature conditions.
Solution Approach 2:
The patent implements a feedback mechanism where the serializer monitors the timing relationship between data and clock signals and automatically adjusts their relative timing. By using the same circuit path for both signals and incorporating delay adjustment capabilities within the serializer, the system dynamically compensates for timing skew caused by power and temperature variations, ensuring reliable data recovery at the receiver.
Data Source
AI summary
A data transmitting device and a flat plate display using the same are disclosed. The data transmitting device includes a clock generator to generate and output a first clock signal and to generate a plurality of second clocks signals having different phases; a serializer to convert parallel image data and a dot clock input at a slow speed to high speed serial data and high speed clock according to the first and second clocks outputted from the clock generator and to output the high speed serial image data and the high speed clock; and a signal converter to convert the serial image data and the high speed clock outputted from the serializer into differential signals and to output the differential signals.