Shared Signal Line for Display Timing Control

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Solution Overview

Problem

Current display devices require multiple signal channels for transmitting control signals, which increases complexity and reduces efficiency, particularly in handling clock training and reception state feedback between the timing controller and data driver.

Innovation Solution

A display device design that uses a shared bidirectional signal line to transmit both the clock training signal and the reception state feedback, reducing the number of channels needed by employing a dual-level control signal system within the same signal line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple signal channels are used for transmitting control signals between timing controller and data driver, then the reliability of signal transmission is improved, but the device complexity increases

Engineering Contradiction:
Improvesignal transmission reliabilityVSAvoidnumber of signal channels
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the clock training signal transmission and reception state feedback into a single shared bidirectional signal line. The timing controller transmits the clock training signal through the shared signal line, and the data driver returns the reception state feedback through the same line, eliminating the need for separate channels for each function.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared signal line serves multiple functions: it acts as both a unidirectional transmission channel for clock training signals and a bidirectional channel for reception state feedback. This multi-functional design reduces the total number of signal channels while maintaining reliable communication between the timing controller and data driver.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If a shared bidirectional signal line is used for transmitting both clock training signal and feedback, then the number of channels is reduced, but the difficulty of signal transmission control increases

Engineering Contradiction:
Improvenumber of signal channelsVSAvoidsignal transmission control
Core Design Contradiction:
Device complexityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent segments the signal transmission into distinct time periods: a first period for transmitting the clock training signal from the timing controller to the data driver, and a second period for transmitting the reception state feedback from the data driver to the timing controller. This temporal segmentation allows the shared signal line to handle bidirectional communication without signal conflicts.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The shared signal line operates dynamically by switching its function based on the current time period. During the first period, it functions as a unidirectional transmission line for clock training signals. During the second period, it functions as a bidirectional line for feedback transmission. This dynamic reconfiguration enables efficient use of a single shared channel.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11107385B2Display device
Publication Date: 2021.08.31 SAMSUNG DISPLAY CO LTD
  • US11107385B2 patent drawing
  • US11107385B2 patent drawing
  • US11107385B2 patent drawing

AI summary

A display device includes a timing controller which supplies a clock training signal through a data clock signal line and a first control signal through a shared signal line in a first period of one frame, and supplies image data through the data clock signal line in a second period of the one frame, a data driver provided with data driving circuits which generate a clock signal based on the clock training signal and the first control signal in the first period, and generate data voltages based on the clock signal and the image data in the second period, and a pixel part which receives the data voltages from the data driver. The data driver may supply a second control signal indicating a reception state of the data driver to the timing controller through the shared signal line in the second period.