Display Device Shielding Structure for Parasitic Capacitance Reduction
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Solution Overview
Problem
Organic light emitting display devices face issues with parasitic capacitances that affect pixel luminance and image quality, necessitating a solution to reduce or prevent these capacitances.
Innovation Solution
The display device incorporates a unique layout with a conductive member overlapping the data line, a driving voltage line, and a control line with detour portions, along with a semiconductor member and insulation layers to minimize parasitic capacitance by shielding the data line and maintaining a constant voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional layout without shielding structures is used, then the device complexity is low, but parasitic capacitance increases causing luminance fluctuations and image quality degradation
Solution Approach 1:
A conductive member (shield electrode) is introduced as an intermediary element between the data line and control line/main line. This shield electrode, connected to a constant potential (ELVDD), acts as an electromagnetic shield to reduce parasitic capacitance and prevent crosstalk between signal lines, thereby improving image quality without fundamentally changing the device architecture
Solution Approach 2:
The conductive member is connected to a constant potential (ELVDD) to create an equipotential region between the data line and control line. By maintaining the shield electrode at a fixed potential, the patent eliminates voltage differences that would otherwise cause parasitic capacitance and crosstalk, ensuring stable signal transmission
2Object-affected harmful factors
If the control line is routed directly without detour portions, then the layout is simple, but parasitic capacitance between the control line and data line increases
Solution Approach 1:
The control line is segmented into multiple sections with detour portions that route around the data line. By dividing the control line into segments separated by detour portions, the patent reduces the overlapping area between the control line and data line, thereby minimizing parasitic capacitance while maintaining electrical connectivity
Solution Approach 2:
The control line is routed in a three-dimensional manner by introducing detour portions that extend in the vertical direction (crossing over or under the data line). This dimensional approach allows the control line to maintain its function while reducing planar overlap with the data line, thus decreasing parasitic capacitance
3Object-affected harmful factors
If the conductive member overlaps the data line without insulation, then the shielding effect is maximized, but short circuit risk increases
Solution Approach 1:
An insulation layer is introduced as an intermediary barrier between the conductive member (shield electrode) and the data line. This insulation layer prevents direct electrical contact and potential short circuits while allowing the conductive member to maintain its electromagnetic shielding function, thus balancing safety and effectiveness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance, stabilizes the driving voltage, and enhances image quality by preventing luminance fluctuations and color deviations in the display.
Implementation Method 1
a conductive member including a portion connected to the first driving voltage line and overlapping the first data line... effectively reduces parasitic capacitance
Data Source
AI summary
A display device according to an exemplary embodiment of the present invention includes: a scan line extending in a first direction; a data line crossing the scan line and transmitting a data signal; a driving voltage line crossing the scan line and transmitting a driving voltage; a conductive member including a portion connected to the driving voltage line and overlapping the data line, wherein a first insulation layer is interposed between the conductive member and the data line; and a control line including a plurality of main line portions each extending in the first direction, and a detour portion that is located between two of the plurality of main line portions that are adjacent one another in a plan view, wherein the detour portion connects the two adjacent main line portions together, wherein a part of the detour portion is located between the conductive member and the driving voltage line in the plan view.