Display Shift Register Circuit for Narrow Bezel and Stable Gate Signals

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Solution Overview

Problem

The existing shift register circuits in display panels have a complex structure, leading to a large size and non-conducive narrow bezel design, and unstable gate drive signals affecting display quality.

Innovation Solution

A simplified shift register circuit with a first and second control module, and first and second output modules, where the potential of one node directly controls another, reducing complexity and size, and ensuring stable signal output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a conventional shift register circuit structure is used, then the gate driving function is achieved, but the circuit size becomes large and the structure becomes complex

Engineering Contradiction:
Improvecircuit structure complexityVSAvoidshift register circuit size
Core Design Contradiction:
Device complexityVSArea of stationary object

Solution Approach 1:

The shift register circuit is divided into two independent units: a first unit with first control module and first output module, and a second unit with second control module and second output module. Each unit handles different signal levels independently, reducing overall circuit complexity and size while maintaining full functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The control nodes of the first and second output modules are merged into a single shared control node. This merging reduces the number of control nodes from two to one, simplifying the circuit structure and reducing the area occupied by the shift register circuit.

Inventive Principle:
Principle #5Merging (Combining)

2Area of stationary object

If a conventional shift register circuit structure is used, then the gate driving function is achieved, but the non-display region size increases

Engineering Contradiction:
Improvenon-display region sizeVSAvoidcircuit structure complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

By segmenting the shift register into two compact units that share control nodes, the overall circuit footprint is reduced, allowing the shift register to be placed in a smaller non-display region while maintaining the required driving functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Merging the control nodes of both output modules into a single shared node reduces the total number of control elements required, thereby reducing the area needed in the non-display region and enabling narrow bezel design.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If a conventional shift register circuit is used, then signal output is achieved, but the signal stability is poor

Engineering Contradiction:
Improvesignal stabilityVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The circuit is segmented into two units that operate independently on different signal levels. This segmentation prevents signal interference and crosstalk between different signal paths, improving signal stability and accuracy while keeping each unit's structure simple.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The control nodes are merged into a single shared node that simultaneously controls both output modules. This unified control mechanism ensures synchronized operation and consistent signal timing, improving signal stability without requiring additional complex control circuitry.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12488739B2Shift register circuit applied in a shift register for display, shift register, display panel and display device
Publication Date: 2025.12.02 XIAMEN TIANMA DISPLAY TECH CO LTD
  • US12488739B2 patent drawing
  • US12488739B2 patent drawing
  • US12488739B2 patent drawing

AI summary

A shift register circuit includes a first control module for controlling the potential of a first node in response to an input signal and a clock signal; a first output module for controlling the transmission path of a first level signal to a signal output terminal in response to the potential of the first node; a second control module for controlling a second level signal to be transmitted to a second node when the first level signal is transmitted to the signal output terminal and control the first level signal to be transmitted to the second node when the first level signal stops being transmitted to the signal output terminal; and a second output module for controlling the transmission path of the second level signal to the signal output terminal in response to the potential of the second node.