Display Panel Shift Register Timing for Low-Power High Refresh
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Solution Overview
Problem
Existing display panels face challenges in reducing power consumption without compromising display quality, particularly in high-refresh-rate scenarios such as videos and games, due to inaccurate gate driving signal transitions in shift registers.
Innovation Solution
A display panel with a cascaded N-stage shift register system that includes shift control, shift output, selection control, output control, and signal output modules, allowing for sequential shifting of enable level start times and flexible control of gate driving signals to ensure accurate signal transmission and display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the refresh rate of the display panel is increased to improve display quality for videos and games, then the display quality is improved, but the power consumption of the display panel increases
Solution Approach 1:
The shift register implements dynamic enable level timing where the enable level duration is adaptively adjusted based on whether it is the first stage (longer duration) or subsequent stages (shorter duration). This dynamic timing adjustment allows the display to maintain high refresh rates for improved display quality while reducing the overall active signaling time, thereby lowering power consumption.
Solution Approach 2:
The patent changes the timing parameters of the enable level signal across different stages of the shift register. The first stage maintains the enable level for a longer duration to ensure accurate signal initiation, while subsequent stages use a shorter enable level duration. This parameter optimization allows the system to achieve high refresh rates for better display quality while minimizing the total active time of signaling operations, thus reducing power consumption.
2Reliability
If the enable level time of the shift signal is extended to ensure accurate signal transmission, then the signal transmission accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent applies different enable level durations to different stages of the shift register based on their specific functional requirements. The first stage receives a longer enable level duration to ensure accurate signal initiation and transmission, while subsequent stages receive a shorter enable level duration. This localized optimization ensures signal transmission accuracy where needed while reducing power consumption in stages that require less signaling time.
3Use of energy by moving object
If the refresh rate is lowered to reduce power consumption, then the power consumption is reduced, but the display quality of videos and games is affected
Solution Approach 1:
The shift register implements periodic signaling with optimized enable level durations that allow the display to operate at high refresh rates. By using shorter enable level durations in subsequent stages compared to the first stage, the system can maintain high refresh rates for improved display quality of videos and games while the reduced signaling time per frame lowers overall power consumption.
Data Source
AI summary
Display panel and display device are provided. The display panel includes driving circuit including a cascaded N-stage shift register. A stage of the cascaded N-stage shift register includes: shift control module, configured to at least receive an input signal and control signals of a first node and a second node; shift output module, configured to at least receive the signals of the first node and the second node, and control a shift signal; selection control module, configured to at least receive the shift signal and a selection control signal, and control a time for transmitting the selection control signal to the third node; output control module, configured to at least receive the shift signal and a signal of a third node, and control a signal of a fourth node; and signal output module, configured to at least receive the signal of the fourth node, and control a gate driving signal.