Display Panel Shift Register Layout for Narrow Bezel Wiring
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Solution Overview
Problem
The existing shift register circuits in display panels require a large amount of connection lines, leading to increased wiring complexity and a larger bezel size, which hinders the achievement of a narrow bezel design.
Innovation Solution
The display panel design includes cascaded shift register unit groups, where each group consists of two shift register units, with signal and reset connections optimized to reduce the number of connection lines, allowing for sequential scan signal enable level shifting and simplified wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional shift register units are connected with separate connection lines for each signal, then signal transmission reliability is improved, but wiring complexity and bezel size increase
Solution Approach 1:
The patent combines multiple connection lines into a shared connection line that serves multiple shift register units. Specifically, one connection line is used to transmit signals from multiple first shift register units to multiple second shift register units, and another connection line transmits reset signals from multiple second shift register units to multiple first shift register units. This merging approach reduces the total number of connection lines while maintaining signal transmission reliability through the shared infrastructure.
Solution Approach 2:
The connection lines are designed to serve multiple functions and multiple shift register units simultaneously. A single connection line acts as a universal pathway for signal transmission between groups of shift register units, rather than having dedicated one-to-one connections. This multi-functionality reduces wiring complexity while ensuring reliable signal distribution across the display panel.
2Measurement precision
If more connection lines are used for shift register units, then signal transmission accuracy is improved, but the space required in the non-display region increases
Solution Approach 1:
Multiple connection lines are merged into shared connection lines that serve multiple shift register units. Instead of having separate connection lines for each signal between individual units, the patent uses shared connection lines that carry signals between groups of units, significantly reducing the total number of lines and the space they occupy in the non-display region.
Solution Approach 2:
The patent reorganizes the connection architecture from a one-to-one dimensional mapping to a many-to-many dimensional mapping. By grouping shift register units and using shared connection lines, the design transitions from linear individual connections to a more efficient dimensional arrangement that reduces spatial requirements in the non-display region.
3Reliability
If separate connection lines are provided for each shift register unit, then connection reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple individual connection lines into shared connection lines that serve multiple shift register units. This consolidation reduces the total number of connection lines that need to be manufactured and assembled, thereby lowering manufacturing costs while maintaining connection reliability through the shared connection infrastructure.
Solution Approach 2:
The design discards the redundant individual connection lines for each shift register unit and recovers the resources by implementing shared connection lines. This approach eliminates unnecessary manufacturing complexity and cost while preserving the essential function of reliable signal transmission between shift register units.
Data Source
AI summary
Provided display panel includes display region and non-display region. The display region includes display units arranged in array and scan signal lines. At least part display units in same row share respective scan signal line. The non-display region includes shift register circuit and connection lines. The shift register circuit includes cascaded shift register unit groups each including at least two shift register units each including signal input terminal, reset control terminal, and signal output terminal. Signal output terminal of first shift register unit in (i+1)-th shift register unit group electrically connected to signal input terminal of respective shift register unit in (i+2)-th shift register unit group through same connection line. Signal output terminal of second shift register unit in (i+1)-th shift register unit group electrically connected to reset control terminal of respective shift register unit in i-th shift register unit group through same connection line. i is positive integer.