Display Device Signal Generator Reduces Wiring Complexity

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Solution Overview

Problem

Current display devices require a large number of wirings between the timing controller and signal generator, which increases the size of the panel driver and complicates the driving process.

Innovation Solution

A display device that generates a vertical start signal and multiple gate clock signals based on two reference clock signals, reducing the need for additional wiring and simplifying the panel driver by using a timing controller, signal generator, and gate driver to produce these signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If multiple control signals are transmitted from timing controller to signal generator, then the display device can be driven, but the number of wirings increases and panel driver size increases

Engineering Contradiction:
Improvedriving capabilityVSAvoidpanel driver size
Core Design Contradiction:
Ease of operationVSArea of stationary object

Solution Approach 1:

The signal generator is designed to generate multiple control signals (vertical start signal, gate clock signal, inverted gate clock signal) from a single set of reference clock signals. This multi-functional approach eliminates the need for separate wiring for each control signal, as all signals are produced internally by the signal generator based on the received reference clocks, thereby reducing the number of wirings and panel driver size while maintaining full driving capability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The reference clock signals serve as an intermediary that carries essential timing information from the timing controller to the signal generator. Instead of transmitting multiple separate control signals, the system uses these reference clock signals as a compact mediator that enables the signal generator to produce all necessary control signals internally, thus reducing wiring requirements

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If multiple control signals are transmitted from timing controller to signal generator, then the display device can be driven, but the number of wirings increases

Engineering Contradiction:
Improvedriving capabilityVSAvoidwiring complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The signal generator performs multiple functions by generating vertical start signals, gate clock signals, and inverted gate clock signals from a single pair of reference clock signals. This consolidation reduces wiring complexity as all control signals are produced internally without requiring separate external wiring for each signal

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The reference clock signals act as an intermediary that simplifies the wiring structure. Instead of complex wiring for multiple control signals, the system uses simple wiring to transmit only the reference clock signals, which then enable the signal generator to produce all other control signals internally

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10997885B2Display device and method of driving the same
Publication Date: 2021.05.04 SAMSUNG DISPLAY CO LTD
  • US10997885B2 patent drawing
  • US10997885B2 patent drawing
  • US10997885B2 patent drawing

AI summary

A display device includes a display panel including a plurality of pixels, a timing controller that generates a first reference clock signal having a first pulse and a second reference clock signal having a second pulse, a signal generator that generates a vertical start signal of which an activation period starts in response to the first pulse and the second pulse and generates a gate clock signal and an inverted gate clock signal based on the first pulse and the second pulse, and a gate driver that generates a gate signal based on the vertical start signal, the gate clock signal, and the inverted gate clock signal and provides the gate signal to the pixels.