Display Circuit Board Signal Layout for Lower PLG Temperature
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Solution Overview
Problem
The increasing size, refresh rate, and display resolution of display products lead to higher panel loads, causing the Patterned Line on Glass (PLG) temperature to rise, which can result in the burning of the Polarizer (POL) and affect the liquid crystal characteristics.
Innovation Solution
A circuit board design with signal lines that include a main body and output branches, where the line width of the main body is greater than the sum of the line widths of the output branches, effectively reducing the resistance and increasing heat dissipation, thereby lowering the PLG temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the display resolution and refresh rate are increased, then the display quality is improved, but the panel load increases causing PLG temperature to rise
Solution Approach 1:
The signal line is segmented into a main body portion and multiple branch portions. The main body has a greater line width than the sum of all branch portions, creating a stepped structure that reduces resistance in the high-current clock signal path while distributing connections to multiple GOA circuits through the branches.
Solution Approach 2:
Different portions of the signal line have different line widths optimized for their specific functions. The main body portion has a larger line width to handle high current with lower resistance, while the branch portions have smaller line widths suitable for individual GOA circuit connections. This local optimization reduces overall power loss and heat generation.
2Loss of energy
If the line width of signal lines is increased to reduce resistance, then the heat dissipation is improved, but the occupied area increases
Solution Approach 1:
The signal line is divided into a main body with larger width for heat dissipation and multiple narrower branches for area efficiency. This segmentation allows the high-current path to have adequate width for thermal management while the overall structure occupies less area than a uniformly wide line would require.
Solution Approach 2:
Multiple branch signal lines are merged into a single main body line that connects to the COF. This merging allows the individual branches to have smaller widths (reducing total area) while the combined main body provides sufficient cross-sectional area for heat dissipation and current carrying capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces the PLG temperature, preventing POL burning and ensuring the reliability and performance of the display substrate by reducing heat transfer to the active area.
Implementation Method 1
the current of the clock line (Clock, CLK) rises sharply, and the temperature of the Patterned Line on Glass (PLG) between the Chip on Film (COF) and the gate drive circuit also increases simultaneously
Implementation Method 2
a line width of the main body is greater than a sum of line widths of all the output branches... effectively reducing the resistance and increasing heat dissipation
Data Source
AI summary
A circuit board includes an input side and an output side oppositely arranged, and the output side is configured to electrically connect to a display substrate. The circuit board includes a plurality of signal lines extending in a direction from the input side to the output side. Each of the plurality of signal lines includes a main body and a plurality of output branches. Each of the plurality of output branches is connected to one end of the main body close to the output side and has a same line width. A line width of the main body is greater than a sum of line widths of all the output branches belonging to same signal line.