Display Signal Line Layout for Lower Parasitic Capacitance

The patent applies dimensionality change by transitioning from a planar two-dimensional arrangement of signal lines to a three-dimensional stacked configuration. Multiple signal lines (first, second, third, and fourth lines) are arranged on different layers vertically above the base layer, allowing signal transmission paths to be separated in the vertical dimension. This reduces parasitic capacitance between adjacent signal lines while maintaining a compact footprint, effectively resolving the contradiction between reducing harmful electromagnetic interference and maintaining device simplicity.

The patent segments the signal line arrangement into distinct functional groups: first and second signal lines on one side of the pixel, and third and fourth signal lines on the other side. This segmentation allows each group to be optimized independently for transmittance, with insulation layers strategically placed between specific line pairs. The segmented approach reduces the need for high-precision positioning across all lines simultaneously, as each segment can be manufactured with standard precision tolerances while achieving cumulative transmittance improvement.

The patent applies local quality by creating distinct functional zones with different characteristics: the first region provides high transmittance for sensing operations, the second region serves as a transition zone with moderate transmittance, and the third region is optimized for pixel display quality. This zonal approach allows each region to be independently optimized for its specific function, enabling the display region to achieve high display quality while the sensing region maintains high sensitivity, thus resolving the contradiction between display quality and sensing sensitivity.