Display Substrate Signal Line Layout for Gate Signal Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display technologies face issues with synchronization of gate control signals from driver chips on opposite sides of the display region, leading to potential abnormal display due to uneven signal output and process variations.
Innovation Solution
The display substrate design includes multiple signal lines with sub-signal lines connected to different driver chips through signal access pins, ensuring consistent output signals by integrating these lines in a peripheral region with specific configurations such as double-layer wiring and connection lines to reduce resistance and static electricity accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If driver chips are placed on opposite sides of the display region to provide gate control signals, then the display area can be fully covered with control signals, but signal synchronization and consistency deteriorate due to process variations and uneven signal output
Solution Approach 1:
The patent merges the signal lines from opposite sides of the display region into a single integrated signal line structure. Specifically, first and second signal lines extending from opposite sides are connected through a connection structure in the peripheral region, forming a unified signal path that ensures synchronized gate control signals across the entire display area, eliminating the synchronization issues caused by separate driver chips on opposite sides.
Solution Approach 2:
The patent introduces an intermediary connection structure in the peripheral region that mediates between the signal lines from opposite sides. This connection structure acts as a bridge that equalizes the signal paths and ensures consistent signal transmission, serving as a mediator that resolves the synchronization conflict between signals from different sides.
2Reliability
If signal lines extend across the peripheral region to connect opposite sides, then signal synchronization is improved, but line resistance and static electricity accumulation increase
Solution Approach 1:
The patent segments the long signal lines into multiple shorter sections by introducing connection structures at strategic points in the peripheral region. This segmentation reduces the total resistance by creating multiple parallel paths and minimizes static electricity accumulation by breaking up continuous long conductive paths into manageable segments with reduced capacitance.
Solution Approach 2:
The patent transitions the signal line configuration from a two-dimensional planar extension across the peripheral region to a three-dimensional structure utilizing multiple layers and vertical connections. This dimensional change allows signal lines to be routed through different planes, reducing the effective path length, minimizing resistance, and providing better control over static electricity discharge paths.
Data Source
AI summary
Disclosed is a display substrate including a base substrate, at least one first signal line, and multiple signal access pins. The base substrate includes a display region and a peripheral region located at a periphery of the display region. The peripheral region includes a first peripheral region, a second peripheral region, a third peripheral region, and a fourth peripheral region which are communicated sequentially. The first signal line is located in the peripheral region and includes at least two sub-signal lines connected with each other. The multiple signal access pins are located in a signal access region. Each sub-signal line of the first signal line extends to the signal access region and is connected with at least one signal access pin in the signal access region so as to be connected with a driver chip through the signal access pin.