Display Device Signal Internal Links for Uniform Loading

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Solution Overview

Problem

Conventional display devices experience signal interference and uneven loading effects due to closely embedded conducting wires, affecting display quality and preventing a narrow frame design.

Innovation Solution

The display device incorporates a substrate with first and second signal lines and internal links, where internal links are electrically connected to corresponding signal lines, ensuring equal loading effects by modifying signal line layouts or adjusting RC delays, allowing for a uniform loading effect and enabling a narrow frame design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conducting wires are embedded too close to each other, then device complexity is reduced, but signal interference and uneven loading effects occur

Engineering Contradiction:
Improveconductor layout complexityVSAvoidsignal interference
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces dummy conductors as intermediary elements between adjacent signal conductors. These dummy conductors are identical in structure to real conductors and are positioned to create symmetric capacitive loading. The dummy conductors act as mediators that balance the electrical environment, ensuring that both real conductors experience equal loading effects even when physically close to each other, thereby eliminating signal interference without increasing overall device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of stationary object

If conducting wires are embedded too close to each other, then area is reduced, but uneven loading effects affect display quality

Engineering Contradiction:
Improvedisplay areaVSAvoidloading effect uniformity
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent applies local quality by making the dummy conductors have identical dimensions and properties to the real conductors. This ensures that at each local position where conductors are embedded close together, the loading effect is uniformly distributed. The dummy conductors are strategically placed only where needed to balance the capacitive loading, creating local symmetry that ensures uniform loading effects across the entire display area while maximizing the usable display area.

Inventive Principle:
Principle #3Local quality

3Object-affected harmful factors

If peripheral region is enlarged to dispose conducting wires, then signal interference is reduced, but frame width increases

Engineering Contradiction:
Improvesignal interferenceVSAvoidframe width
Core Design Contradiction:
Object-affected harmful factorsVSLength of stationary object

Solution Approach 1:

The patent transitions from a one-dimensional solution (increasing peripheral region area) to a two-dimensional solution (using dummy conductors within the existing conductor layout). Instead of simply expanding the peripheral region to reduce signal interference, the invention introduces dummy conductors that are integrated into the conductor pattern itself, utilizing the vertical dimension and spatial arrangement within the display area to achieve uniform loading effects. This approach maintains a narrow frame while effectively managing signal interference through strategic conductor placement and symmetry.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8723758B2Display device having signal internal links
Publication Date: 2014.05.13 AU OPTRONICS CORP
  • US8723758B2 patent drawing
  • US8723758B2 patent drawing
  • US8723758B2 patent drawing

AI summary

A display device includes a substrate, a plurality of first signal lines, a plurality of second signal lines, and a plurality of first signal internal links. The first signal lines and the second signal lines are crossed and disposed in a display region of the substrate. The first signal internal links are disposed in the display region of the substrate, wherein each of the first signal internal links is electrically connected to a corresponding first signal line and disposed between two adjacent second signal lines. Each of the first signal internal links intersects the first signal lines, and the number of intersection points of each of the first signal internal links and the first signal lines is the same.