Display Substrate Signal Line Overlap for High-PPI Pixel Layout
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Solution Overview
Problem
The increasing demand for high-density pixel displays in display devices leads to higher manufacturing costs, hindering the widespread adoption of high image quality technologies due to complex process requirements.
Innovation Solution
A display substrate design with overlapping signal lines in different conductive layers, optimizing the layout of pixel driving circuits to achieve high PPI while reducing manufacturing complexity, utilizing a stack design for initialization and control signal lines with partial overlap ratios between 60% to 100%, and incorporating multiple transistors for efficient pixel driving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-density pixel layout is implemented to improve image quality, then PPI increases, but manufacturing cost significantly increases
Solution Approach 1:
The patent implements overlapping signal lines in different conductive layers (first conductive layer and second conductive layer) to achieve three-dimensional spatial arrangement. This allows signal lines to overlap in the planar view while being separated vertically, reducing the required area per pixel and enabling high PPI without proportionally increasing manufacturing complexity
Solution Approach 2:
The patent divides the signal line routing into multiple conductive layers, with initialization voltage signal lines and control signal lines placed in different layers. This segmentation allows independent optimization of each layer's routing and reduces the complexity of planar routing, making high-density pixel layouts more manufacturable
2Area of stationary object
If signal lines are overlapped in different conductive layers to reduce area, then pixel density increases, but signal interference may occur
Solution Approach 1:
The patent implements time-division multiplexing where initialization voltage signals and control signals are applied in different time periods. The initialization voltage signal line provides signals in a first time period while the control signal line provides signals in a second time period, ensuring signals do not overlap in time despite spatial overlap in different conductive layers
Solution Approach 2:
The patent uses different conductive layers as intermediaries to separate initialization voltage signal lines and control signal lines. This spatial separation in the vertical dimension (different conductive layers) combined with temporal separation (different time periods) prevents direct electromagnetic interference while maintaining compact pixel area
3Measurement precision
If pixel driving circuits are optimized for high PPI, then display quality improves, but process requirements become more complex
Solution Approach 1:
The patent merges initialization voltage signal lines and control signal lines in the planar view by allowing their orthographic projections to overlap. This is achieved by placing them in different conductive layers, effectively combining the space usage of both signal line types without increasing the pixel area, thus enabling high PPI with manageable process complexity
Data Source
AI summary
Provided are a display substrate and a display device. The display substrate includes: a base substrate; sub-pixels; light emitting elements; pixel driving circuits; an initialization voltage signal line extending in the first direction; and a control signal line partially extending in the first direction. In a frame of driving the pixel driving circuits of a row of sub-pixels, the control signal controls, in at least one first time period, at least two transistors of the pixel driving circuit to turn on, the initialization voltage signal is provided to the pixel driving circuit in a second time period, and the first and second time periods are separated in a timing sequence. An orthographic projection of the initialization voltage signal line on the base substrate overlaps at least partially with that of the control signal line located on a different layer, with an overlapping rate of 60% to 100%.


