Display Panel Source Driver Layout for Higher Clocked Data Rates
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Solution Overview
Problem
The rate of source drivers in display panels is limited by a bottleneck and difficult to improve due to high-frequency clock signals being susceptible to loading and glass-based transistors having lower operating speeds than silicon-based transistors.
Innovation Solution
The source driver is integrated into an insulating substrate and divided into multiple shift register groups, each controlled by clock lines with different phases and frequencies, allowing for lower frequency operation and reducing the frequency load on individual shift registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single clock line controls all shift registers, then the source driver can operate at high rate, but the clock signal is susceptible to loading and the rate cannot be improved further
Solution Approach 1:
The patent divides the shift registers into multiple groups (first shift register group, second shift register group, etc.) and assigns different clock lines to each group. This segmentation allows each clock line to control fewer shift registers, reducing the loading effect on individual clock signals while maintaining or increasing the overall source driver rate through parallel operation of multiple groups.
2Ease of manufacture
If glass-based transistors are used in the source driver, then manufacturing cost is reduced, but the operating speed is lower than silicon-based transistors
Solution Approach 1:
By segmenting the shift registers into multiple groups controlled by different clock lines, the patent enables parallel operation that compensates for the lower speed of glass-based transistors. The multiple clock lines with different phases allow simultaneous driving of multiple shift register groups, effectively increasing the overall data transmission rate despite the inherent speed limitation of glass-based transistor technology.
3Productivity
If multiple clock lines with different phases are used, then the source driver rate can be increased, but the device complexity increases
Solution Approach 1:
The patent segments the shift registers into distinct groups that can be independently controlled by different clock lines. This segmentation strategy, while introducing multiple clock lines, organizes the complexity in a manageable way where each clock line manages a specific subset of shift registers, making the overall system complexity acceptable compared to the benefit of increased data transmission rate through parallel operation.
Data Source
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AI summary
The present disclosure provides a semiconductor device and a display panel, the semiconductor device includes an insulating substrate, at least one data input terminal, and a plurality of clock lines. By dividing a plurality of shift registers into a plurality of shift register groups, each clock line of the plurality of clock lines controls a rate of a shift register group, and compared with the case of controlling all of the shift registers through a single clock line, a rate of the shift register may be easily increased to a higher value as frequencies of a plurality of clock signals increase.