Display Device Source Line Segmentation for High Frame Rate Operation
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Solution Overview
Problem
High-resolution display devices with large screen sizes and high frame frequencies face challenges in productivity and operational difficulty due to the low field-effect mobility of transistors using amorphous silicon or metal oxide, which can struggle with heavy loads and complex wiring configurations.
Innovation Solution
A display device design that includes multiple source and gate lines with overlapping conductive layers and semiconductor layers, utilizing amorphous silicon or metal oxide transistors, which reduces parasitic capacitance and allows for high-resolution displays without dividing source and gate lines, enabling efficient operation at higher frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors using amorphous silicon or metal oxide are used, then productivity and ease of formation over large substrates are improved, but field-effect mobility deteriorates
Solution Approach 1:
The patent divides the display device into multiple pixel regions, with each region having its own source line and gate line. This segmentation allows the heavy load to be distributed across multiple lighter source lines, enabling high frame frequency operation while using transistors with lower field-effect mobility (amorphous silicon or metal oxide).
Solution Approach 2:
The patent introduces a third direction by arranging source lines in the first direction and gate lines in the second direction, creating a mesh-like structure. This dimensional arrangement allows for better signal distribution and reduced load on individual lines, supporting high frame frequency operation.
2Measurement precision
If resolution and screen size are increased, then display quality is improved, but load on source lines and gate lines increases
Solution Approach 1:
The patent segments the source lines and gate lines into multiple separate lines that are distributed across the display device. Each line serves a specific pixel region, which reduces the load on each individual line while maintaining high resolution and screen size.
Solution Approach 2:
The patent implements dynamic scanning of source lines and gate lines, where lines are activated in sequence rather than simultaneously. This dynamic approach allows the display to operate at high frame frequencies by updating pixel regions progressively, reducing the instantaneous load on each line.
3Power
If source line and gate line are divided, then load on each line is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments source lines and gate lines into multiple separate lines arranged in a mesh pattern. This segmentation reduces the load on each line while maintaining a relatively simple manufacturing process by using standard thin-film transistor fabrication techniques.
4Speed
If frame frequency is increased, then display smoothness is improved, but operational difficulty increases
Solution Approach 1:
The patent divides the display into multiple pixel regions with separate source lines and gate lines, allowing for parallel processing of signal updates. This segmentation enables high frame frequency operation by distributing the updating task across multiple lines, reducing operational difficulty.
Solution Approach 2:
The patent uses dynamic scanning of source and gate lines to achieve high frame frequencies. By sequentially activating different lines rather than updating everything simultaneously, the system maintains operational simplicity while achieving smooth display at high frame rates.
Data Source
AI summary
To achieve a display device that is suitable for increasing in size and to provide a high-resolution display device. In the display device, three or more adjacent gate lines are supplied with the same selection signal. Three or more pixels that adjoin in the column direction are connected to different source lines. In each of the pixels, a transistor including a semiconductor layer is disposed. An inner source line among three or more source lines is disposed to overlap with a conductive layer that functions as a pixel electrode. Part of the semiconductor layer of the transistor is provided between the outer source line and a source line adjacent to the outer source line.