Display Device Stacked Conductive Layers Reducing Wire Resistance
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Solution Overview
Problem
Existing light emitting diode displays face challenges in reducing wire resistance and improving display quality, which affects their performance and efficiency.
Innovation Solution
The display device incorporates a specific layer structure including a substrate, conductive layers, insulation layers, active patterns, and a capacitor configuration that reduces wire resistance by using overlapping gate electrodes and scan lines, and a third conductive layer with a lower resistance than the second conductive layer, allowing for improved capacitance and reduced load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wire structures are used in LED displays, then device complexity is reduced, but wire resistance increases and display quality deteriorates
Solution Approach 1:
The patent transitions from planar wire structures to three-dimensional stacked conductive layers. Multiple conductive layers (first, second, third conductive layers) are arranged vertically with insulation layers in between, creating a multi-dimensional wiring architecture that reduces resistance while managing complexity through systematic layering
Solution Approach 2:
The patent implements nested conductive patterns where third conductive layer patterns are positioned within regions defined by second conductive layer patterns. The capacitor electrode overlaps with the driving gate electrode, forming a nested capacitor structure that integrates multiple functions within confined spatial regions
2Reliability
If wire resistance is reduced by increasing conductor size, then electrical performance improves, but device area increases
Solution Approach 1:
Instead of increasing conductor width in the plane, the patent extends conductivity into the vertical dimension by stacking multiple conductive layers. The third conductive layer is positioned below the second conductive layer in certain regions, creating parallel conduction paths that reduce resistance without expanding the device footprint
Solution Approach 2:
The patent combines multiple conductive layers into integrated wiring structures. The first, second, and third conductive layers are merged through vertical stacking with insulation layers, forming unified conductive pathways that achieve lower resistance while maintaining compact area through efficient space utilization
3Reliability
If capacitance is increased to improve load handling, then energy storage improves, but device complexity increases
Solution Approach 1:
The capacitor is formed by merging the driving gate electrode (in the second conductive layer) with the capacitor electrode (in the third conductive layer) through vertical stacking. The insulation layer between these electrodes serves as the capacitor dielectric, creating an integrated capacitor structure that combines storage function with the existing gate structure
Solution Approach 2:
The third conductive layer serves dual purposes: it provides wiring functions for signal transmission and forms capacitor electrodes for energy storage. The driving gate electrode also serves as one electrode of the capacitor, allowing the same structure to fulfill multiple functions simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the resistance of the display device, enhancing its performance by improving the capacitance and load handling, thereby improving display quality and efficiency.
Implementation Method 1
the capacitor electrode and the driving gate electrode form a capacitor
Data Source
AI summary
A display device includes a first conductive layer, a first insulation layer disposed on the first conductive layer, and active patterns disposed on the first insulation layer. The display device further includes a second conductive layer disposed on the active patterns and including a first gate electrode that overlaps a channel region of the active patterns and a driving gate electrode, a second insulation layer disposed on the second conductive layer, a third conductive layer including a capacitor electrode and at least one scan line disposed on the second insulation layer, a third insulation layer disposed on the third conductive layer, and an electrode layer including a first electrode disposed on the third insulation layer. The first electrode is connected to the capacitor electrode, the capacitor electrode overlaps the driving gate electrode, and the capacitor electrode and the driving gate electrode form a capacitor.