Display Device Storage Voltage Uniformity
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Solution Overview
Problem
In liquid crystal displays, the application of a constant voltage to each pixel through wiring results in voltage delays, reduced aperture ratio and transmittance due to additional wiring, and potential shorts at intersections of gate and data lines, leading to inconsistent display quality, especially when viewed from the side.
Innovation Solution
A display device design incorporating multiple switching elements and assistant storage voltage lines that connect main storage voltage lines, preventing voltage delays and maintaining a constant storage voltage across pixels, while minimizing additional wiring and avoiding intersections that could cause shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a storage voltage line is extended to transmit storage voltage to each pixel, then the storage voltage can be applied to each pixel, but the magnitude of the storage voltage varies according to the position of the pixel due to voltage delay
Solution Approach 1:
The storage voltage line is divided into multiple segments with separate voltage application points. Instead of using a single continuous line from one source, multiple storage voltage lines are provided, each extending from different sources to different pixel regions, ensuring uniform voltage magnitude across all pixels regardless of position.
Solution Approach 2:
Multiple intermediate storage voltage sources are introduced throughout the display device. These intermediary sources act as local voltage replenishment points, compensating for voltage drops that would occur in a single-line configuration and ensuring consistent voltage delivery to all pixels.
2Reliability
If separate wiring is added to transmit storage voltage to each pixel, then voltage can be applied to pixels, but the aperture ratio or transmittance is reduced
Solution Approach 1:
The storage voltage lines are merged with or integrated into the existing gate line structure. By combining the storage voltage transmission function with the existing gate line infrastructure, additional dedicated wiring is minimized, thereby preserving the aperture ratio and light transmittance of the display device.
Solution Approach 2:
The gate lines are designed to serve dual functions: both as gate signal transmission lines and as storage voltage lines. This multi-functionality eliminates the need for separate dedicated storage voltage wiring, maintaining high aperture ratio while ensuring reliable voltage delivery to all pixels.
3Ease of manufacture
If gate line and data line intersect, then wiring can be routed to pixels, but the cell gap is decreased at intersection positions making shorts to common electrode more likely
Solution Approach 1:
The cell gap is designed with local variations: standard gap dimensions in most regions and increased gap dimensions specifically at wireline intersection positions. This localized modification maintains manufacturability while preventing shorts at critical intersection points where multiple conductors cross.
Solution Approach 2:
The design anticipates potential short circuit risks at intersection points by pre-establishing increased clearance distances. The larger cell gap at intersection positions acts as a preventive measure, cushioning against the harmful effect of shorts before they can occur during device operation.
4Manufacturing precision
If multiple switching elements and assistant storage voltage lines are added to prevent voltage delays, then voltage uniformity is improved, but device complexity increases
Solution Approach 1:
The assistant storage voltage lines are integrated with the existing gate line structure, merging multiple functions into unified conductors. This reduces the need for completely separate additional wiring systems, thereby limiting the increase in device complexity while still achieving voltage uniformity across all pixels.
Data Source
AI summary
A display device includes gate lines, data lines, first wires and second wires extending in the directions of the gate lines and data lines, and pixels having a first subpixel and a second subpixel each. The first subpixel has a first subpixel electrode and a first switching element, and the second subpixel has a second subpixel electrode and second and third switching elements. The control terminals of the three switching elements are connected to the same gate line, and the input terminals of the first and second switching elements are connected to the same data line. The first and second switching elements have output terminals connected to the first and second subpixel electrodes, respectively. The second switching element's output terminal connects to the third switching element, which has an output terminal connected to a second wire. The first wires and the second wires are connected in a pixel.