Display Substrate Layout for Higher Aperture Ratio Pixels

The patent applies dimensionality change by implementing a top-gate transistor structure where the gate electrode is positioned above the active layer rather than beside it. This vertical arrangement allows the gate line to extend in the row direction while the data line extends in the column direction, enabling more efficient space utilization within the pixel. The via holes connecting different layers add a third dimension (vertical connectivity) to the wiring scheme, effectively increasing the aperture ratio by reducing the area occupied by conductive structures in the planar view.

The patent segments the wiring structure into multiple functional layers: the first conductive layer contains data lines and electrode lines, the second conductive layer contains gate lines and common electrodes, and via holes provide vertical connections between layers. This segmentation allows different wiring functions to be distributed across layers, reducing planar overlap and minimizing the area occupied by conductive structures, thereby increasing the aperture ratio while maintaining high resolution.

The patent utilizes vertical layering to separate wiring functions, with gate lines in the second conductive layer and data lines in the first conductive layer. This three-dimensional arrangement allows for adequate line widths in each layer without excessive planar overlap, reducing the need for extremely narrow lines and thereby lowering manufacturing precision requirements while still achieving high aperture ratios.

The patent employs a top-gate transistor structure where the gate electrode is formed above the active layer before final pixel electrode deposition. This preliminary positioning of the gate structure allows for optimized spacing and reduced overlap with data lines and pixel electrodes, enabling larger effective aperture areas without requiring ultra-precise control of line widths during subsequent manufacturing steps.

The patent implements light shielding functionality in the vertical dimension by positioning the common electrode and black matrix structures in the second conductive layer above the pixel electrodes. This vertical arrangement allows the black matrix to effectively shield light from below while occupying minimal planar area, as the shielding function is achieved through vertical positioning rather than wide horizontal extensions, thereby increasing aperture ratio while maintaining light shielding effectiveness.

The patent introduces the common electrode as an intermediary structure that serves dual functions: it provides electrical connection for the liquid crystal modulation and simultaneously acts as part of the light shielding system when combined with the black matrix. This intermediary structure enables effective light blocking with reduced line widths by distributing the shielding function across multiple components in the vertical stack.